2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS)最新文献

A motion detection pixel system using an inductorless UWB transmitter on standard 0.35µm/CMOS technology 采用标准0.35µm/CMOS技术的无电感超宽带发射机的运动检测像素系统

2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519056

Marcelo Macchi da Silva, J. F. Neto, L. C. Moreira, J. Swart

{"title":"A motion detection pixel system using an inductorless UWB transmitter on standard 0.35µm/CMOS technology","authors":"Marcelo Macchi da Silva, J. F. Neto, L. C. Moreira, J. Swart","doi":"10.1109/LASCAS.2013.6519056","DOIUrl":"https://doi.org/10.1109/LASCAS.2013.6519056","url":null,"abstract":"This paper presents a CMOS pixel motion detector based on a current-mode APS (Active Pixel Sensor) topology with wireless capability using an Impulse Radio - Ultra Wide Band (IR-UWB) in standard 0.35μm CMOS technology for applications in image sensor networks. A pixel was designed with a transmission gate to control one copier cell in order to compare different integration times. The pixel output is a digital signal proportional to the difference between the two currents. The proposed IR-UWB has a simple architecture, without inductors and carrier modulators. It is based on parallel pulse generator blocks that produce Gaussian pulses, and a pulse shaping stage which adjusts the pulse amplitude, below the FCC -41.3dBm floor. The transmitter exhibits as main characteristics: output pulse of 408ps wide at 4.90GHz, and voltage amplitude of 144mVpp, an average power is only of 7.15μW/pulse at 170MHz PRF (Pulse Repetition Frequency). The whole circuit has been simulated using LTSpice and the results demonstrate the circuit capability to operate as a motion detector. The complete circuit pixel occupies a very small area of 120μm × 115μm.","PeriodicalId":190693,"journal":{"name":"2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124922912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A current-starved inverter-based differential amplifier design for ultra-low power applications 超低功耗应用的电流匮乏型逆变器差分放大器设计

2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519040

William Wilson, Tom Chen, Ryan Selby

{"title":"A current-starved inverter-based differential amplifier design for ultra-low power applications","authors":"William Wilson, Tom Chen, Ryan Selby","doi":"10.1109/LASCAS.2013.6519040","DOIUrl":"https://doi.org/10.1109/LASCAS.2013.6519040","url":null,"abstract":"As silicon feature sizes decrease, more complex circui try arrays can now be contrived on a single die. This increase in the number of on-chip devices per unit area results in increased power dissipation per unit area. In order to meet certain power and operating temperature specifications, circuit design necessitates a focus on power efficiency, which is especially important in systems employing hundreds or thousands of instances of the same device. In large arrays, a slight increase in the power efficiency of a single component is heightened by the number of instances of the device in the system. This paper proposes a fully differential, low-power current-starving inverter-based amplifier topology designed in a commercial 0.18μm process. This design achieves 46dB DC gain and a 464 kHz uni ty gain frequency with a power consumption of only 145.32nW at 700mV power supply vol tage for ultra-low power, low bandwidth applications. Higher bandwidth designs are also proposed, including a 48dB DC gain, 2.4 MHz unity-gain frequency amplifier operating at 900mV wi th only 3.74μW power consumption.","PeriodicalId":190693,"journal":{"name":"2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125155838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30

A programmable charge pump voltage converter for implantable medical devices in a HV technology 一种可编程电荷泵电压转换器，用于植入式医疗设备的高压技术

2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519060

J. Gak, M. Miguez, A. Arnaud

引用次数: 8

Design of an OTA-Miller for a 96dB SNR SC multi-bit Sigma-Delta modulator based on gm/ID methodology 基于gm/ID方法的96dB信噪比SC多位Sigma-Delta调制器的OTA-Miller设计

2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519051

H. Cubas, J. Soares

引用次数: 7

Algorithms for energy efficient reconstruction of a process with a multihop Wireless Sensor Network 基于多跳无线传感器网络的过程节能重构算法

2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519004

F. da Rocha Henriques, LISANDRO LOVISOLO, M. Rubinstein

引用次数: 3

A power optimized decimator for sigma-delta data converters 用于sigma-delta数据转换器的功率优化十进制

2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519018

D. Carvalho, J. Navarro

引用次数: 4

Design of synchronous pipeline digital systems operating in double-edge of the clock 同步管道数字系统的设计工作在双边时钟

2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519068

D. L. Oliveira, T. Curtinhas, L. Faria, L. Romano

{"title":"Design of synchronous pipeline digital systems operating in double-edge of the clock","authors":"D. L. Oliveira, T. Curtinhas, L. Faria, L. Romano","doi":"10.1109/LASCAS.2013.6519068","DOIUrl":"https://doi.org/10.1109/LASCAS.2013.6519068","url":null,"abstract":"In contemporaneous digital systems the fetch by performance is critical, many times is accomplished through of the use of the pipeline control. In these systems the activity of the clock signal is a major energy consumer. It is responsible for 15% to 45% of the total consumed energy. Once reducing the activity of the clock signal, it is possible not only a reduction of the considered energy, but also a reduction of clock skew problems and electromagnetic iteration. An interesting strategy to achieve this goal is to design the synchronous digital system to operate in transitions of both edges of the clock signal (double-edge triggered - DET), once it allows a 50% reduction in the frequency of the clock signal, although showing the same processing rate data. In this paper it is proposed a method that synthesizes synchronous digital systems with pipeline control that operate on both edges of the clock signal, using only flip-flops sensitive to a single edge of the clock signal (single-edge triggered flip-flops-SET-FF) as components of the state memory. The proposed method presents very good potential to reduce the problems associated with the clock, has a high probability of practical implementation with low penalty on area.","PeriodicalId":190693,"journal":{"name":"2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127946396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Optimization of a self-converging algorithm at assembly level to improve SEU fault-tolerance 优化装配级自收敛算法以提高单单元容错性

2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519033

Greicy Marques-Costa, W. Mansour, F. Pancher, R. Velazco, A. Bui, D. Sohier

引用次数: 1

Systematic configuration of coarsely discretized 3D EM solvers for reliable and fast simulation of high-frequency planar structures 系统配置粗离散三维电磁求解器，实现高频平面结构的可靠、快速仿真

2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519093

J. Rayas-Sánchez, Z. Brito-Brito, Juan C. Cervantes-González, Carlos A. Lopez

{"title":"Systematic configuration of coarsely discretized 3D EM solvers for reliable and fast simulation of high-frequency planar structures","authors":"J. Rayas-Sánchez, Z. Brito-Brito, Juan C. Cervantes-González, Carlos A. Lopez","doi":"10.1109/LASCAS.2013.6519093","DOIUrl":"https://doi.org/10.1109/LASCAS.2013.6519093","url":null,"abstract":"Accurate simulation of microstrip and other planar structures at very high frequencies usually requires employing full-wave electromagnetic (EM) solvers. For planar circuits, 2.5D EM solvers are especially suited and easy to configure. However, in some cases, planar circuits are required to be simulated in 3D solvers. On the other hand, low-resolution discretization in 3D solvers is necessary when coarse models are employed for direct EM optimization, for instance, in space mapping methodologies, or in surrogate-based modeling techniques. In this work, we propose a systematic methodology to find a suitable 3D EM solver configuration when low-resolution meshing is needed for reliable and fast simulation of planar structures. We illustrate how improper configuration of the 3D EM solver might lead to significant alteration of the inherent structure's EM response, as well as to numerical noise that affects the parameterized usage of these models, such as in direct EM optimization. Our technique is illustrated by a couple of classical microstrip filters simulated with a commercially available 3D full-wave EM solver.","PeriodicalId":190693,"journal":{"name":"2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133848774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Design of NCL gates with the ASCEnD flow 基于ASCEnD流的NCL闸门设计

2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519002

Matheus T. Moreira, C. Oliveira, Ricardo C. Porto, Ney Laert Vilar Calazans

引用次数: 17