2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS)最新文献_第2页

A real time high definition architecture for the Variable-Length Reference Frame Decoder 可变长度参考帧解码器的实时高清晰度结构

2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519062

D. Silveira, M. Porto, L. Agostini

引用次数: 0

Accuracy vs simulation speed trade-off enhancements in the generation of chaotic attractors 混沌吸引子生成中精度与仿真速度的权衡增强

2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6518988

C. Sánchez-López, J. Mendoza-Lopez, C. Muñiz-Montero, L. A. Sánchez-Gaspariano, J. Muñoz-Pacheco

{"title":"Accuracy vs simulation speed trade-off enhancements in the generation of chaotic attractors","authors":"C. Sánchez-López, J. Mendoza-Lopez, C. Muñiz-Montero, L. A. Sánchez-Gaspariano, J. Muñoz-Pacheco","doi":"10.1109/LASCAS.2013.6518988","DOIUrl":"https://doi.org/10.1109/LASCAS.2013.6518988","url":null,"abstract":"In this paper, the trade-off between accuracy and simulation speed in the generation of muti-scroll chaotic attractors at 1-D is analyzed and improved. In a first step, a macromodel based on bipolar transistors and passive elements is used to model the behavior of Opamps, and later on they are used to approach the behavior of all nonlinear system. Hspice simulations are executed to generate chaotic attractors in the phase plane and time-series. CPU-time used during the solution of the chaotic system is computed. In a second stage, a simple and accurate nonlinear model, which includes the most influential performance parameters for Opamps, is coded in C++ and it is used to generate a nonlinear system of equations, which models the behavior of all chaotic system. CPU-time is also computed. Because chaotic waveforms generated have a random behavior, statistical tests are used to measure the similitude/accuracy between two random variables during a long time. Our results indicate that chaotic waveforms can swiftly be generated by using the simple but accurate model for Opamps without the accuracy worsens, independently of the initial conditions of the chaotic system.","PeriodicalId":190693,"journal":{"name":"2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125056572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Development of a stereo vision measurement architecture for an underwater robot 水下机器人立体视觉测量体系的研制

2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519001

Camilo Sánchez-Ferreira, J. Y. Mori, C. Llanos, E. Fortaleza

{"title":"Development of a stereo vision measurement architecture for an underwater robot","authors":"Camilo Sánchez-Ferreira, J. Y. Mori, C. Llanos, E. Fortaleza","doi":"10.1109/LASCAS.2013.6519001","DOIUrl":"https://doi.org/10.1109/LASCAS.2013.6519001","url":null,"abstract":"Underwater robotics tasks are considered very critical, mainly because of the hazardous environment. The embedded systems for this kind of robots should be robust and fault-tolerant. This paper describes the development of a system for embedded stereo vision in real-time, using a hardware/software co-design approach. The system is capable to detect an object and measure the distance between the object and the cameras. The platform uses two CMOS cameras, a development board with a low-cost FPGA, and a display for visualizing images. Each camera provides a pixel-clock, which are used to synchronize the processing architectures inside the FPGA. For each camera a hardware architecture has been implemented for detecting objects, using a background subtraction algorithm. Whenever an object is detected, its center of mass is calculated in both images, using another hardware architecture to do that. The coordinates of the object center in each image are sent to a soft-processor, which computes the disparity and determines the distance from the object to the cameras. A calibration procedure gives to the soft-processor the capability of computing both disparities and distances. The synthesis tool used (Altera Quartus II) estimates that the system consumes 115.25mW and achieves a throughput of 26.56 frames per second (800×480 pixels). These synthesis and the operation results have shown that the implemented system is useful to real-time distance measurements achieving a good precision and an adequate throughput, being suitable for real-time critical operation.","PeriodicalId":190693,"journal":{"name":"2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128287341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A low voltage CMOS voltage reference based on partial compensation of MOSFET threshold voltage and mobility using current subtraction 基于MOSFET阈值电压部分补偿和电流减法迁移率的低压CMOS电压基准

2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519024

L. Toledo, P. Petrashin, W. Lancioni, F. Dualibe, Luis Rafael Canali

引用次数: 5

Behavioral modeling of continuous-time ΣΔ modulators in matlab/simulink 连续时间ΣΔ调制器在matlab/simulink中的行为建模

2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6518992

P. Aguirre, V. Camargo, H. Klimach, A. Susin, C. Prior

引用次数: 8

Low cost and high throughput FME interpolation for the HEVC emerging video coding standard 低成本和高吞吐量FME插值的HEVC新兴视频编码标准

2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519017

Vladimir Afonso, Henrique Maich, L. Agostini, Denis Franco

引用次数: 36

A system clock precision frequency to code converter for low power supply dependence ROIC 一种用于低电源依赖性ROIC的系统时钟精度频码转换器

2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6518994

R. Aragonés, J. Oliver, C. Ferrer

{"title":"A system clock precision frequency to code converter for low power supply dependence ROIC","authors":"R. Aragonés, J. Oliver, C. Ferrer","doi":"10.1109/LASCAS.2013.6518994","DOIUrl":"https://doi.org/10.1109/LASCAS.2013.6518994","url":null,"abstract":"This paper presents the frequency-to-code converter for a low power consumption ReadOut Integrated Circuit (ROIC). It allows conditioning and acquiring capacitive sensors signals that complements the front-end of the acquisition platform with very high resolution. The design consists of a temperature compensated voltage reference circuit (bandgap) coupled to a low power relaxation oscillator that adjusts the input signal of the Capacitive-toFrequency converter (CtoF). The bandgap, ensures the correct power supply dependence compensation of the CtoF. This sensing acquisition board, conforms the front-end of the frequency to digital processing architecture developed for this ROIC. For this circuitry, a novel frequency to code converter with very high precision conversion and low relative quantification error has been designed. Moreover, a Microblaze embedded processor has been used in this architecture in order to linearize the CtoF response and to control the whole acquisition process. Finally the output of the processing board is transmitted to an external monitoring unit via an internal UART.","PeriodicalId":190693,"journal":{"name":"2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125384057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

A dual core low power microcontroller with openMSP430 architecture for high reliability lockstep applications using a 180 nm high voltage technology node 采用openMSP430架构的双核低功耗微控制器，适用于采用180 nm高压技术节点的高可靠性锁步应用

2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519085

S. Sondon, P. Mandolesi, F. Masson, P. Julián, F. Palumbo

引用次数: 0

A new delay distribution model to take long-term degradation into account 一种新的考虑长期退化的延迟分布模型

2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519047

S. Tsukiyama, M. Fukui, T. Kambe

{"title":"A new delay distribution model to take long-term degradation into account","authors":"S. Tsukiyama, M. Fukui, T. Kambe","doi":"10.1109/LASCAS.2013.6519047","DOIUrl":"https://doi.org/10.1109/LASCAS.2013.6519047","url":null,"abstract":"The long-term degradation due to aging such as NBTI (Negative Bias Temperature Instability) is a hot issue in the current circuit design using nanometer process technologies, since it causes a delay fault in the field. In order to resolve the problem, we must estimate delay variation caused by long-term degradation in design stage, but over estimation must be avoided so as to make timing design easier. If we can treat such a variation statistically, and if we treat it together with delay variations due to process variability, then we can reduce over margin in timing design. Moreover, such a statistical static timing analyzer treating process variability and long-term degradation together help us to select an appropriate set of paths for which field testing are conducted to detect delay faults. In this paper, we propose a new delay model taking long-term degradation into account for statistical static timing analysis, and propose an algorithm for finding the statistical maximum, which is one of key operations in statistical static timing analysis. We also show a few experimental results demonstrating the effect of the algorithm.","PeriodicalId":190693,"journal":{"name":"2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126357725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A design technique for distributed dual-band bandpass filters 分布式双带带通滤波器的设计技术

2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) Pub Date : 2013-05-23 DOI: 10.1109/LASCAS.2013.6519080

Thiago P. R. Goes, R. N. Lima, L. Martinez, F. Sousa

引用次数: 1