Behavioral modeling of continuous-time ΣΔ modulators in matlab/simulink

In this paper, a behavioral model of Continuous-Time (CT) Sigma-Delta Modulators (ΣΔMs) is presented. The non-idealities of the ΣΔM such as operational amplifiers finite parameters (DC gain, slew-rate, voltage saturation and unity gain frequency), excess loop delay, clock jitter and quantizer offset are modeled in Matlab/Simulink environment providing accurate time-based simulations. For demonstration purposes, a 3rd order single bit CT ΣΔM topology with Non-Return to Zero (NRZ) and another one with Switched-Capacitor Resistor (SCR) DAC feedback are simulated and have their performance degradation due to non-idealities analyzed. The effects of the non-idealities are clearly seen when compared to the ideal modulator. Also, key design specifications for the functional building blocks could be derived from simulations with the proposed models.