A strategy for mapping reconfigurable cores in NoCs

Abstract

In the last years, Field programmable gate-arrays (FPGAs) with partial reconfiguration capabilities have raised interest in the implementation of dynamically reconfigurable systems (DSRs). For dealing with the issue of communication between reconfigurable and fixed partitions, Networks-on-Chip (NoCs) have gained importance in DSR architectures. The mapping of cores in NoCs aims to find the best topological location onto the NoC, such that the metrics of interest can be greatly optimized. In this paper, the mapping strategy for reconfigurable cores into NoCs is presented and the sensibility in respect to the cost function is evaluated. Results confirm the need for mapping optimization algorithms aimed to reduce both the traffic and power consumption.