Nature Electronics最新文献_第7页

Out-of-plane Ruddlesden–Popper ferroelectrics catch a break 面外的Ruddlesden-Popper铁电体得到了突破

IF 42.3 1区工程技术

Nature Electronics Pub Date : 2026-07-06 DOI: 10.1038/s41928-026-01665-6

Weijia Guo, Zhenxing Yue

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Author Correction: Parity–time symmetry and exceptional points in electronic circuits 作者更正：电子电路中的奇偶时间对称性和异常点

IF 42.3 1区工程技术

Nature Electronics Pub Date : 2026-06-29 DOI: 10.1038/s41928-026-01671-8

Lucas J. Fernández-Alcázar, Qi Zhong, Ulrich Kuhl, Pai-Yen Chen, Ramy El-Ganainy, Tsampikos Kottos

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Spectrometers in miniature 微型光谱仪

IF 42.3 1区工程技术

Nature Electronics Pub Date : 2026-06-26 DOI: 10.1038/s41928-026-01668-3

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Efficient training of neuromorphic electronics 神经形态电子学的有效训练

IF 42.3 1区工程技术

Nature Electronics Pub Date : 2026-06-26 DOI: 10.1038/s41928-026-01631-2

Shuangming Yang, Jianshi Tang, Tianhang Zhou, Bernabe Linares-Barranco, Giacomo Indiveri, Xinhu Zheng, Mostafa Rahimi Azghadi, Badong Chen

{"title":"Efficient training of neuromorphic electronics","authors":"Shuangming Yang, Jianshi Tang, Tianhang Zhou, Bernabe Linares-Barranco, Giacomo Indiveri, Xinhu Zheng, Mostafa Rahimi Azghadi, Badong Chen","doi":"10.1038/s41928-026-01631-2","DOIUrl":"10.1038/s41928-026-01631-2","url":null,"abstract":"Neuromorphic electronics can provide in-memory computing systems with low power consumption by emulating key principles of the brain. However, their practical capabilities are limited by a number of challenges, including device non-ideality, limited training accuracy and insufficient adaptability. Here we explore the development of training approaches for neuromorphic electronics, including digital, mixed-signal and emerging neuromorphic electronics. We examine the characteristics and advantages of different training strategies, including off-chip training with on-chip inference, on-chip training and inference, and hybrid offline–online training strategies. We consider the challenges that must be addressed in terms of advanced training, standardized benchmarks and hardware–software co-design, and highlight applications where such efficient training of neuromorphic electronics could be of particular value. This Review examines the development of training strategies for neuromorphic electronics—including digital, mixed-signal and emerging neuromorphic electronics—analysing the characteristics and advantages of offline, online and hybrid training methods, and identifying key challenges and opportunities for future advances.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"9 6","pages":"594-610"},"PeriodicalIF":42.3,"publicationDate":"2026-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148336866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Industrial reliability testing of transistor gate dielectrics 晶体管栅极电介质的工业可靠性试验

IF 42.3 1区工程技术

Nature Electronics Pub Date : 2026-06-24 DOI: 10.1038/s41928-026-01644-x

Ernest Y. Wu, Tibor Grasser, Mario Lanza

{"title":"Industrial reliability testing of transistor gate dielectrics","authors":"Ernest Y. Wu, Tibor Grasser, Mario Lanza","doi":"10.1038/s41928-026-01644-x","DOIUrl":"10.1038/s41928-026-01644-x","url":null,"abstract":"Transistors are currently undergoing a reinvention due to the stagnation of lateral scaling, the advance of three-dimensional stacking and the introduction of novel nanomaterials such as two-dimensional materials. A critical issue in the development of novel transistors is gate dielectric reliability, as the dielectric needs to withstand high electrical fields and block charge transport to guarantee correct device functioning. However, while attempts have been made in the academic literature to benchmark the figures of merit of transistors, the methodologies proposed for the study of gate dielectrics typically do not match industrial requirements. Here we explore how to evaluate the reliability of a dielectric material in an industry-relevant manner. We examine how industry benchmarks the performance of gate dielectrics in silicon transistors, how to collect and analyse gate dielectric reliability data to extract meaningful and industry-relevant conclusions, and how to apply this to two-dimensional transistors using gate dielectrics such as CaF2 and hexagonal boron nitride. We provide, in particular, a data processing protocol to extract lifetime-specific maximum allowed use voltage from ramped voltage stress, and provide an Excel file as a simple tool to carry out this extraction. This Perspective examines how industry benchmarks the performance of gate dielectrics in silicon transistors, how to collect and analyse gate dielectric reliability data to extract meaningful and industry-relevant conclusions, and how to apply this to two-dimensional transistors.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"9 7","pages":"726-732"},"PeriodicalIF":42.3,"publicationDate":"2026-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148305227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Solution-processable two-dimensional hexagonal copper indium selenide semiconductors 溶液可加工二维六方硒化铜铟半导体

IF 42.3 1区工程技术

Nature Electronics Pub Date : 2026-06-24 DOI: 10.1038/s41928-026-01661-w

Shengqi Wang, Peigen Zhang, Yongping Dai, Jing He, Jifeng Ge, Junying Xue, Wenjie Li, Ruihao Tan, Tingyi Xia, Yanming Liu, He Tian, Zhaoyang Lin

{"title":"Solution-processable two-dimensional hexagonal copper indium selenide semiconductors","authors":"Shengqi Wang, Peigen Zhang, Yongping Dai, Jing He, Jifeng Ge, Junying Xue, Wenjie Li, Ruihao Tan, Tingyi Xia, Yanming Liu, He Tian, Zhaoyang Lin","doi":"10.1038/s41928-026-01661-w","DOIUrl":"10.1038/s41928-026-01661-w","url":null,"abstract":"Solution-processable two-dimensional semiconductors could be used for the cost-effective fabrication of large-area electronic devices. However, compared with two-dimensional materials made using high-temperature chemical vapour deposition methods, they exhibit much lower electrical performance. Here we report the solution-processable fabrication of wafer-scale two-dimensional layered copper indium selenide (CuIn5Se8) semiconductors with high mobility values. The air-stable solution-based ink formulation and film assembly allow four-inch CuIn5Se8 thin films to be deposited in the ambient air environment. By elucidating the impact of a reversible water adsorption process on electrical performance, a moderate annealing step is developed to eliminate surface water molecules. The resulting CuIn5Se8 transistors exhibit an average electron mobility of 155 cm2 V−1 s−1 and an on/off ratio of 107 with a small current hysteresis. Furthermore, the robust transistor operation and small device-to-device variation enable the integration of over 100 transistors into a prototypical microprocessor that can process digital signals at a frequency of 2.2 kHz. Wafer-scale and air-stable semiconducting films of two-dimensional copper indium selenide can be made from monolayer ink deposition and annealing, creating transistors with an average mobility of 155 cm2 V−1 s−1 and a microprocessor containing over 100 devices.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"9 9","pages":"1027-1035"},"PeriodicalIF":42.3,"publicationDate":"2026-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148305233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

One way to stack silicon transistors 一种堆叠硅晶体管的方法

IF 42.3 1区工程技术

Nature Electronics Pub Date : 2026-06-23 DOI: 10.1038/s41928-026-01666-5

Katharina Zeissler

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Monolithic three-dimensional integration of heterogeneous electronics for self-powered sensing and processing 用于自供电传感和处理的异构电子的单片三维集成

IF 42.3 1区工程技术

Nature Electronics Pub Date : 2026-06-23 DOI: 10.1038/s41928-026-01624-1

Subir Ghosh, Pranavram Venkatram, Harikrishnan Ravichandran, Rishikesh T. Nair, Yongwen Sun, Lei Ding, Chen Chen, Joan M. Redwing, Yang Yang, Saptarshi Das

{"title":"Monolithic three-dimensional integration of heterogeneous electronics for self-powered sensing and processing","authors":"Subir Ghosh, Pranavram Venkatram, Harikrishnan Ravichandran, Rishikesh T. Nair, Yongwen Sun, Lei Ding, Chen Chen, Joan M. Redwing, Yang Yang, Saptarshi Das","doi":"10.1038/s41928-026-01624-1","DOIUrl":"10.1038/s41928-026-01624-1","url":null,"abstract":"Self-powered microelectronics systems generate energy from ambient sources like light, heat or mechanical vibrations using on-chip devices, and the overall system is designed to minimize its power footprint. These systems can be used to build systems that operate autonomously without an external power source. Such systems are of particular interest in edge computing, internet of things devices and remote-sensing technologies, for which replacing or recharging batteries is impractical. Here we report on a monolithic three-dimensional integrated circuit that stacks graphene transistors in the top tier for low-power chemical sensing, complementary logic circuits based on n-type monolayer molybdenum disulfide (MoS2) and p-type bilayer tungsten diselenide (WSe2) in the middle tier for low-power computing, and an on-chip silicon photovoltaic module in the bottom tier to harvest ambient light. The integrated system, which operates solely on ambient light, can distinguish between various chemical solutions and generate corresponding digital codes in a fully sustainable manner. We also demonstrate the dense integration of data and power vias across the tiers and show that the intertier separation can be reduced to 50 nm. A low-power self-powered integrated system for sensing and computing can be created through the monolithic integration of tiers containing graphene-based chemical sensors, two-dimensional semiconductor-based complementary logic and silicon photovoltaic modules.","PeriodicalId":19064,"journal":{"name":"Nature Electronics","volume":"9 7","pages":"775-787"},"PeriodicalIF":42.3,"publicationDate":"2026-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"148305230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":1,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

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Checking your health during screentime 看屏幕时检查自己的健康状况

IF 42.3 1区工程技术

Nature Electronics Pub Date : 2026-06-23 DOI: 10.1038/s41928-026-01667-4

Matthew Parker

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A silicon chip for water-based parallel DNA synthesis 用于水基平行DNA合成的硅片

IF 42.3 1区工程技术

Nature Electronics Pub Date : 2026-06-19 DOI: 10.1038/s41928-026-01664-7

引用次数: 0