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Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.最新文献

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Characterisation of microfluidic devices 微流体装置的特性
Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002. Pub Date : 2002-04-08 DOI: 10.1109/ICMTS.2002.1193198
D. Bien, S. Mitchell, H. Gamble
{"title":"Characterisation of microfluidic devices","authors":"D. Bien, S. Mitchell, H. Gamble","doi":"10.1109/ICMTS.2002.1193198","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193198","url":null,"abstract":"Silicon micromachining techniques have enabled the fabrication of a wide range of microfluidic components and systems. Given the small volumes of liquid and low flow rates involved, the accurate characterisation of such systems presents a challenge. To date many of the measurements have been performed manually; this is both time consuming and prone to inaccuracies. This paper describes an automated measurement technique and presents results for a surface micromachined valve.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130977916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Influence of probing configuration and data set size for bipolar junction capacitance determination 探测结构和数据集大小对双极结电容测定的影响
Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002. Pub Date : 2002-04-08 DOI: 10.1109/ICMTS.2002.1193184
D. MacSweeney, K. McCarthy, L. Floyd, A. Mathewson, P. Hurley, J. A. Power, S. C. Kelly
{"title":"Influence of probing configuration and data set size for bipolar junction capacitance determination","authors":"D. MacSweeney, K. McCarthy, L. Floyd, A. Mathewson, P. Hurley, J. A. Power, S. C. Kelly","doi":"10.1109/ICMTS.2002.1193184","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193184","url":null,"abstract":"In this paper, the on-wafer measurement of junction depletion capacitance is examined. This work provides an in-depth discussion of possible probing configurations which can be used. It outlines a method to consistently measure the junction capacitances accurately. The results from this method compare favourably with those extracted using S-parameter measurements. Additionally a method is formulated to determine the minimum number of data points required to maintain extraction accuracy.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"295 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133725130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A comparison of extraction techniques for threshold voltage mismatch 阈值电压失配提取技术的比较
Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002. Pub Date : 2002-04-08 DOI: 10.1109/ICMTS.2002.1193202
J. A. Croon, Hans Tuinhout, R. Difrenza, J. Knol, A. J. Moonen, Stefaan Decoutere, Herman Maes, Willy Sansen
{"title":"A comparison of extraction techniques for threshold voltage mismatch","authors":"J. A. Croon, Hans Tuinhout, R. Difrenza, J. Knol, A. J. Moonen, Stefaan Decoutere, Herman Maes, Willy Sansen","doi":"10.1109/ICMTS.2002.1193202","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193202","url":null,"abstract":"In this paper commonly used extraction methods of MOSFET threshold voltage mismatch are compared. The V/sub T/ mismatch is extracted on the exact same device population by four independent characterization groups. Significant differences are observed, which are caused by differences in measurement setup and differences in extraction algorithm. The observed differences are analyzed. In addition merits and limitations of the various techniques are evaluated.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121973080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
A test structure for the design of thermal flow sensors 一种用于热流传感器测试结构的设计
Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002. Pub Date : 2002-04-08 DOI: 10.1109/ICMTS.2002.1193180
N. Sabaté, I. Gràcia, J. Santander, C. Cané
{"title":"A test structure for the design of thermal flow sensors","authors":"N. Sabaté, I. Gràcia, J. Santander, C. Cané","doi":"10.1109/ICMTS.2002.1193180","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193180","url":null,"abstract":"A test structure for the design and optimisation of thermal gas flow sensors has been developed. This test structure provides information about the temperature distribution created around a heating element as well as its modification due to a gas flow, thus permitting to obtain information about the thermal conductivity of the membrane material. Data obtained from the characterisation of the structure can be used in the optimisation of a flow sensor designed for any specific application.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127443572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
CV doping profiling of boron out-diffusion using an abrupt and highly doped arsenic buried epilayer 利用突发性和高掺杂砷埋没涂层的硼向外扩散的CV掺杂分析
Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002. Pub Date : 2002-04-08 DOI: 10.1109/ICMTS.2002.1193176
C. Ortiz, L. Nanver, W. van Noort, Tlm Scholtes, J. Slotboom
{"title":"CV doping profiling of boron out-diffusion using an abrupt and highly doped arsenic buried epilayer","authors":"C. Ortiz, L. Nanver, W. van Noort, Tlm Scholtes, J. Slotboom","doi":"10.1109/ICMTS.2002.1193176","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193176","url":null,"abstract":"The use of CV measurements to profile the electrically active impurity profile of dopants has long been popular as a fast and non-destructive measurement technique. In this work, an n/sup -/p/sup -/n/sup +/ or ip/sup -/n/sup +/ structure is proposed for CV-doping profiling of the tail of boron-doped regions extending into a lightly doped top layer. The usefulness of this method for the evaluation of boron transient enhanced diffusion (TED) effects in Si and Si/sub 1-x/Ge/sub x/ is demonstrated both experimentally and via simulations.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114690734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A test circuit for measuring standard deviations of MOSFET channel conductance and threshold voltage 用于测量MOSFET通道电导和阈值电压的标准偏差的测试电路
Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002. Pub Date : 2002-04-08 DOI: 10.1109/ICMTS.2002.1193172
K. Terada, M. Sumida
{"title":"A test circuit for measuring standard deviations of MOSFET channel conductance and threshold voltage","authors":"K. Terada, M. Sumida","doi":"10.1109/ICMTS.2002.1193172","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193172","url":null,"abstract":"A new test circuit is proposed for measuring the standard deviations of both MOSFET channel conductance and threshold voltage. This test circuit consists of the matrix-shape MOSFET array in which several switches and wiring are added. DC currents flowing through this array are measured, changing the ON/OFF states of the switches, and then the standard deviations are calculated from them.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"163 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120898588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A new test structure and characterization methodology to identify array leakage path in Mask ROM 一种新的测试结构和表征方法来识别掩模ROM中的阵列泄漏路径
Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002. Pub Date : 2002-04-08 DOI: 10.1109/ICMTS.2002.1193169
T. Fan, K.Y. Chan, T. Lu, S. Pan
{"title":"A new test structure and characterization methodology to identify array leakage path in Mask ROM","authors":"T. Fan, K.Y. Chan, T. Lu, S. Pan","doi":"10.1109/ICMTS.2002.1193169","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193169","url":null,"abstract":"The array leakage is a crucial issue while developing ultra high-density planar Mask ROM memories. However, it is hard to identify this leakage and its mechanism using the conventional cell array test structure. It is because that because the cell surface punch leakage, cell bulk leakage, and surface buried drain to buried drain (BD to BD) leakage beyond cell channel region all contribute to the total leakage at the same time. In order to identify these leakage paths and reduce this leakage, we design a new cell array test structure and the characterization methodology is also proposed. The main mechanism of cell leakage has been attributed to the surface BD to BD leakage outside the cell array. This leakage path occurs beneath the exposed silicon surface, which doping concentration near this region is lower than that inside the cell array due to oxide spacer over-etching issue and our PMOS blank N-type pocket implantation.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133750592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High frequency test structures definition for electromagnetic coupling study between two symmetrical inductors. Electrical modelling of the whole coupling between coils 两对称电感器电磁耦合研究的高频试验结构定义。线圈之间整体耦合的电气建模
Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002. Pub Date : 2002-04-08 DOI: 10.1109/ICMTS.2002.1193166
C. Clement, B. van Haaren, D. Gloria
{"title":"High frequency test structures definition for electromagnetic coupling study between two symmetrical inductors. Electrical modelling of the whole coupling between coils","authors":"C. Clement, B. van Haaren, D. Gloria","doi":"10.1109/ICMTS.2002.1193166","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193166","url":null,"abstract":"High frequency test structures for electromagnetic coupling study between two symmetrical inductors are described. Results from the S/sub 12/ parameter measurement are compared to HP-Momentum electromagnetic (EM) simulations and show that coupling doesn't reach -25dB and is smaller than -40dB for a separation distance between coils higher than 200/spl mu/m. An electrical modelling of the whole coupling between coils is proposed and compared with experimental results.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121344215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Novel charge pumping method without using MOS transistor for SOI wafer inspection 不使用MOS晶体管的新型电荷泵送方法用于SOI晶圆检测
Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002. Pub Date : 2002-04-08 DOI: 10.1109/ICMTS.2002.1193194
T. Takami, H. Yoshida, T. Uchihashi, S. Kishino
{"title":"Novel charge pumping method without using MOS transistor for SOI wafer inspection","authors":"T. Takami, H. Yoshida, T. Uchihashi, S. Kishino","doi":"10.1109/ICMTS.2002.1193194","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193194","url":null,"abstract":"A novel charge pumping method without using MOS transistors is proposed for obtaining a spatial distribution of interface traps in an SOI wafer. The proposed method can be performed without fabrication processes for the source/drain of MOS transistors that are essential for conventional charge pumping methods. In this method, Schottky contacts are used instead of the normal source/drain diffused layer. The results demonstrate that the proposed method is effective in applying to SOI wafer inspection.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122895236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Wafer-level characterization of EEPROM tunnel oxide using a fast floating-gate technique and a realistic memory cell-based test structure 利用快速浮栅技术和基于真实记忆单元的测试结构，对EEPROM隧道氧化物进行晶片级表征
Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002. Pub Date : 2002-04-08 DOI: 10.1109/ICMTS.2002.1193187
S. Renard, P. Boivin, J. Autran
{"title":"Wafer-level characterization of EEPROM tunnel oxide using a fast floating-gate technique and a realistic memory cell-based test structure","authors":"S. Renard, P. Boivin, J. Autran","doi":"10.1109/ICMTS.2002.1193187","DOIUrl":"https://doi.org/10.1109/ICMTS.2002.1193187","url":null,"abstract":"We report on the development of a fast characterization technique of EEPROM tunnel oxides based on the floating-gate technique and using a realistic memory cell-based test structure. A sequential measurement procedure and data analysis have been successfully implemented to perform automatic wafer screening of leakage currents in terms of charge retention and tunnel oxide defectivity.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122532145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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