{"title":"利用快速浮栅技术和基于真实记忆单元的测试结构,对EEPROM隧道氧化物进行晶片级表征","authors":"S. Renard, P. Boivin, J. Autran","doi":"10.1109/ICMTS.2002.1193187","DOIUrl":null,"url":null,"abstract":"We report on the development of a fast characterization technique of EEPROM tunnel oxides based on the floating-gate technique and using a realistic memory cell-based test structure. A sequential measurement procedure and data analysis have been successfully implemented to perform automatic wafer screening of leakage currents in terms of charge retention and tunnel oxide defectivity.","PeriodicalId":188074,"journal":{"name":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Wafer-level characterization of EEPROM tunnel oxide using a fast floating-gate technique and a realistic memory cell-based test structure\",\"authors\":\"S. Renard, P. Boivin, J. Autran\",\"doi\":\"10.1109/ICMTS.2002.1193187\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We report on the development of a fast characterization technique of EEPROM tunnel oxides based on the floating-gate technique and using a realistic memory cell-based test structure. A sequential measurement procedure and data analysis have been successfully implemented to perform automatic wafer screening of leakage currents in terms of charge retention and tunnel oxide defectivity.\",\"PeriodicalId\":188074,\"journal\":{\"name\":\"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-04-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMTS.2002.1193187\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2002 International Conference on Microelectronic Test Structures, 2002. ICMTS 2002.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.2002.1193187","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Wafer-level characterization of EEPROM tunnel oxide using a fast floating-gate technique and a realistic memory cell-based test structure
We report on the development of a fast characterization technique of EEPROM tunnel oxides based on the floating-gate technique and using a realistic memory cell-based test structure. A sequential measurement procedure and data analysis have been successfully implemented to perform automatic wafer screening of leakage currents in terms of charge retention and tunnel oxide defectivity.