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2010 IEEE International Conference on Integrated Circuit Design and Technology最新文献

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Through-Silicon-Via stress 3D modeling and design Through-Silicon-Via应力三维建模与设计
2010 IEEE International Conference on Integrated Circuit Design and Technology Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510281
T. Dao, V. Adams
{"title":"Through-Silicon-Via stress 3D modeling and design","authors":"T. Dao, V. Adams","doi":"10.1109/ICICDT.2010.5510281","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510281","url":null,"abstract":"Through-Silicon-Via (TSV) processing is critical to 3D chip stacked integrated circuit (IC) technology. The understanding and management of the induced stresses in silicon due to coefficient of thermal expansion (CTE) mismatch is critical for the successful implementation of this process in circuit design and production. Most TSVs in these applications are copper (Cu) filled. Analysis of Cu-filled TSV induced stress has been reported by Okoro et. al [1], and the proposed stress measurement and model has been reported by Chidambaram et. al. [2].","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134588622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Direct bonding for wafer level 3D integration 直接键合晶圆级3D集成
2010 IEEE International Conference on Integrated Circuit Design and Technology Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510276
L. Di Cioccio, I. Radu, P. Gueguen, M. Sadaka
{"title":"Direct bonding for wafer level 3D integration","authors":"L. Di Cioccio, I. Radu, P. Gueguen, M. Sadaka","doi":"10.1109/ICICDT.2010.5510276","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510276","url":null,"abstract":"3D integration is a promising and fast growing field that addresses the convergence of Moore's Law and more than Moore. 3D integration offers higher performance, higher density, higher functionality, smaller form factor, and potential cost reduction. With this emerging field, new and improved technologies will be necessary to meet the associated manufacturing challenges. This paper describes some 3D building blocks describing oxide to oxide and metal to metal bonding with alignment","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116118260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
ESD protection design for differential low-noise amplifier with cross-coupled SCR 交叉耦合可控硅差分低噪声放大器ESD保护设计
2010 IEEE International Conference on Integrated Circuit Design and Technology Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510294
Chun-Yu Lin, M. Ker, Yuan-Wen Hsiao
{"title":"ESD protection design for differential low-noise amplifier with cross-coupled SCR","authors":"Chun-Yu Lin, M. Ker, Yuan-Wen Hsiao","doi":"10.1109/ICICDT.2010.5510294","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510294","url":null,"abstract":"A new electrostatic discharge (ESD) protection scheme for differential low-noise amplifier (LNA) was proposed in this paper. The new ESD protection scheme, which evolved from the conventional double-diode ESD protection scheme without adding any extra device, was realized with cross-coupled silicon-controlled rectifier (SCR). With the new ESD protection scheme, the pin-to-pin ESD robustness can be improved, which was the most critical ESD-test pin combination for differential input pads. Experimental results had shown that differential LNA with cross-coupled-SCR ESD protection scheme can achieve excellent ESD robustness and good RF performances.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122610668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
CAD for double patterning lithography 双图案光刻CAD
2010 IEEE International Conference on Integrated Circuit Design and Technology Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510279
D. Pan, Jae-Seok Yang, Kun Yuan, Minsik Cho
{"title":"CAD for double patterning lithography","authors":"D. Pan, Jae-Seok Yang, Kun Yuan, Minsik Cho","doi":"10.1109/ICICDT.2010.5510279","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510279","url":null,"abstract":"Nanopatterning with 193nm lithography equipment is one of the most fundamental challenges for future scaling beyond 22nm while the next-generation lithography, such as EUV (Extreme Ultra-Violet) lithography still faces tremendous challenges for mass production in the near future. As a practical solution, double patterning lithography (DPL) has become a leading candidate for 16nm lithography process. DPL poses new challenges for overlay control, layout decomposition, and physical design compliance and optimization. In this paper, we will discuss challenges and some recent results in DPL aware timing analysis, layout decomposition, and layout optimization.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131947438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A robust latch-type sense amplifier using adaptive latch resistance 采用自适应锁存电阻的鲁棒锁存式感测放大器
2010 IEEE International Conference on Integrated Circuit Design and Technology Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510258
T. Song, S. M. Lee, Jaehyouk Choi, Stephen T. Kim, Gyuhong Kim, K. Lim, J. Laskar
{"title":"A robust latch-type sense amplifier using adaptive latch resistance","authors":"T. Song, S. M. Lee, Jaehyouk Choi, Stephen T. Kim, Gyuhong Kim, K. Lim, J. Laskar","doi":"10.1109/ICICDT.2010.5510258","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510258","url":null,"abstract":"A latch-type sense amplifier (SA) utilizing adaptive resistance technique is proposed. With adaptively adjusted resistance in a latch path, the proposed SA can compensate for an erroneous voltage drop in bit-lines induced by bit-cell leakage current. The simulation shows that the sense amplifier margin (SM) is improved in the presence of mismatches. The SA test chip is fabricated in a 0.18-μm CMOS technology showing the SM improvement of 6% to 15% at various supply voltages.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128377535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A top-down approach for substrate noise assessment flow in mixed-signal and SOC designs 混合信号和SOC设计中基板噪声评估流程的自顶向下方法
2010 IEEE International Conference on Integrated Circuit Design and Technology Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510270
Hazem Hegazy, E. Hegazi, N. Sabry, H. Ragaie
{"title":"A top-down approach for substrate noise assessment flow in mixed-signal and SOC designs","authors":"Hazem Hegazy, E. Hegazi, N. Sabry, H. Ragaie","doi":"10.1109/ICICDT.2010.5510270","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510270","url":null,"abstract":"In this paper, a new substrate noise checking methodology is proposed. We adopt a pragmatic approach in solving the ever complex substrate noise problem. At the full chip level, simulator's capacity is the bottleneck. In order to simplify simulators task, abstraction should be applied on different portions of the problem. Clearly, three portions have been recognized and segregated: Substrate noise generation, propagation and reception. Noise generation is considered to be the biggest contributor especially in larger designs. The larger the number of substrate noise generators, the larger the propagation network that connects to prospect receptors. Accordingly, the first challenge is to separate the injectors from receptors. The second would be the aggregation of all injectors' effects on the receptors' side. In our new top-down approach, an innovative noise generation methodology is introduced with proper propagation macro-model. With both models combined, full chip substrate noise assessment flow has been achieved and verified versus silicon.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"90 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120836972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Smart power IC simulation of substrate coupled current due to majority and minority carriers transports 智能功率集成电路的基片耦合电流的模拟由于多数和少数载流子传输
2010 IEEE International Conference on Integrated Circuit Design and Technology Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510262
F. L. Conte, J. Sallese, M. Kayal
{"title":"Smart power IC simulation of substrate coupled current due to majority and minority carriers transports","authors":"F. L. Conte, J. Sallese, M. Kayal","doi":"10.1109/ICICDT.2010.5510262","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510262","url":null,"abstract":"This paper presents a new approach for substrate parasitic current simulation in smart power integrated circuit. A new compact modeling approach developed in previous work has been used to create an equivalent substrate schematic. The latter is composed of new components having the peculiarity not to fully recombine minority carrier at their boundary. By the interconnection of these special components in the electrical design, the effect of substrate current is simulated. Having this information early in the design phase will allow design optimization and reduce the risk of costly chip redesign.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126323137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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