A top-down approach for substrate noise assessment flow in mixed-signal and SOC designs

In this paper, a new substrate noise checking methodology is proposed. We adopt a pragmatic approach in solving the ever complex substrate noise problem. At the full chip level, simulator's capacity is the bottleneck. In order to simplify simulators task, abstraction should be applied on different portions of the problem. Clearly, three portions have been recognized and segregated: Substrate noise generation, propagation and reception. Noise generation is considered to be the biggest contributor especially in larger designs. The larger the number of substrate noise generators, the larger the propagation network that connects to prospect receptors. Accordingly, the first challenge is to separate the injectors from receptors. The second would be the aggregation of all injectors' effects on the receptors' side. In our new top-down approach, an innovative noise generation methodology is introduced with proper propagation macro-model. With both models combined, full chip substrate noise assessment flow has been achieved and verified versus silicon.