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2010 IEEE International Conference on Integrated Circuit Design and Technology最新文献

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Novel SER standards: Backgrounds and methodologies 新的SER标准:背景和方法
2010 IEEE International Conference on Integrated Circuit Design and Technology Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510259
E. Ibe, K. Shimbo, Tadanobu Toba, Yoshio Taniguchi, H. Taniguchi
{"title":"Novel SER standards: Backgrounds and methodologies","authors":"E. Ibe, K. Shimbo, Tadanobu Toba, Yoshio Taniguchi, H. Taniguchi","doi":"10.1109/ICICDT.2010.5510259","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510259","url":null,"abstract":"Standard methods to quantify SER susceptibility in memory devices have been established during 2000–2008. JESD89A issued in 2006 covers a wide variety of test methods for terrestrial neutrons and alpha particles. Spallation and (quasi-) monoenergetic neutron tests are among the best options for the SER tests. The methods, however, are being recognized as getting more inaccurate as device scaling proceeds. SER in logic devices is also getting more serious so that standard testing methods have to be established for logic devices. The new standards may include strategies for mitigation of SERs as well. The backgrounds and methodologies to promote new SER standards for device, chip, board layers are discussed in the present paper.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123388841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Dynamic biasing techniques for RF power amplifier linearity and efficiency improvement 动态偏置技术对射频功率放大器线性度和效率的改善
2010 IEEE International Conference on Integrated Circuit Design and Technology Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510253
N. Deltimple, L. Leyssenne, E. Kerhervé, Y. Deval, D. Belot
{"title":"Dynamic biasing techniques for RF power amplifier linearity and efficiency improvement","authors":"N. Deltimple, L. Leyssenne, E. Kerhervé, Y. Deval, D. Belot","doi":"10.1109/ICICDT.2010.5510253","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510253","url":null,"abstract":"Nowadays, mobile handsets have to deal with several challenges. First of all, a good efficiency is essential in order to save power and battery life-time. Then, to cater to multi-standards operation which provide very high data rates, strong linearity performances are mandatory, to the expense of transmit front-end efficiency. As RF Power Amplifiers (PAs) are the most power consuming components, this paper describes an approach of managing the efficiency-linearity trade-off by using dynamic biasing. The dynamic biasing allows a power control of the PA and is brought into play both with an open-loop solution and a closed-loop solution. The main purpose of the paper is to present a description of the circuits developed and their performances in terms of output power, linearity and efficiency. The reconfigurable PAs are dedicated to UMTS-WCDMA and WiFi/WiMAX standards.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124295708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Low power technology/circuit co-development for advanced mobile devices 先进移动设备的低功耗技术/电路联合开发
2010 IEEE International Conference on Integrated Circuit Design and Technology Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510260
G. Yeap
{"title":"Low power technology/circuit co-development for advanced mobile devices","authors":"G. Yeap","doi":"10.1109/ICICDT.2010.5510260","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510260","url":null,"abstract":"Technology options at 45nm and 32/28nm have been optimized for various mobile device applications. Disposable high performance technology is introduced to satisfy both high speed and low power requirement of modern convergence mobile computing and communication device. Dual Core Oxide scheme using SiON/Poly gate stack was used in 45nm. Scaled SiON/Poly gate stack is sufficient for 32/28nm low power/low cost technology, while HK/MG gate stack with strong process induced stress option is needed for high performance technology.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115858404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-speed links for memory interface 存储器接口的高速链路
2010 IEEE International Conference on Integrated Circuit Design and Technology Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510752
J. Sim, Seon-Kyoo Lee, Young-Sik Kim, Y. Sohn, Joo-Sun Choi
{"title":"High-speed links for memory interface","authors":"J. Sim, Seon-Kyoo Lee, Young-Sik Kim, Y. Sohn, Joo-Sun Choi","doi":"10.1109/ICICDT.2010.5510752","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510752","url":null,"abstract":"Memory, as a fundamental component of a system, has been a leading drive for high-speed parallel links, and it requires interface technology providing stable data rate of multi-Gb/s/pin. The highest data rate in memory IO, presented by GDDR5, shows the data rate of up to 6Gb/s/pin with the traditional single-ended signaling on PCB. Further step to higher throughput, however, presents critical problems which must be overcome by taking challenges in packaging, process as well as circuit design. This paper reviews current status of memory interface circuits and introduces several promising interface technologies such as TSV, Wide-IO, inductive coupling, and multiple serial links.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"364 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132867203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Fast Monte Carlo method via reduced sample number and node filtering 快速蒙特卡罗方法通过减少样本数量和节点滤波
2010 IEEE International Conference on Integrated Circuit Design and Technology Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510272
Inhak Han, Lee-eun Yu, Youngsoo Shin
{"title":"Fast Monte Carlo method via reduced sample number and node filtering","authors":"Inhak Han, Lee-eun Yu, Youngsoo Shin","doi":"10.1109/ICICDT.2010.5510272","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510272","url":null,"abstract":"Monte Carlo (MC) method is convenient and robust to estimate timing yield of circuits under the influence of process variations. The important question in MC method is the number of samples while we assure a desired accuracy of yield estimate, which is often addressed using a rule of thumb. Minimum number of samples can be estimated via approximation by a normal distribution, but the provided number may be too small to be used in practice considering that target yield, which is used to derive the number, is unknown. Chebyshev's inequality has been used to derive a sample number, but the number is too large this time. We develop a new expression, which provides the sample number that is much closer to the minimum (3× to 8×) compared to the number provided by Chebyshev's inequality (5× to 15×). We also propose a simple node filtering algorithm, where we identify the nodes that are likely to affect timing yield; the simulation with each MC sample can handle only a fraction of circuit elements as a result. Reducing the number of MC samples and simulating only selected nodes together yield 27× to 125× speedup over standard MC method.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116887742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Narrowing the margins with elastic clocks 用弹性时钟缩小边缘
2010 IEEE International Conference on Integrated Circuit Design and Technology Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510273
J. Cortadella, L. Lavagno, Djavad Amiri, J. Casanova, C. Macián, F. Martorell, Juan A. Moya, L. Necchi, D. Sokolov, E. Tuncer
{"title":"Narrowing the margins with elastic clocks","authors":"J. Cortadella, L. Lavagno, Djavad Amiri, J. Casanova, C. Macián, F. Martorell, Juan A. Moya, L. Necchi, D. Sokolov, E. Tuncer","doi":"10.1109/ICICDT.2010.5510273","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510273","url":null,"abstract":"The continuous shrinking of process geometries increases variability and demands for conservative margins that have a negative impact on performance. With conventional clocks, the cycle period has to be defined to accommodate the worst-case variations during the lifetime of the circuit. Elastic Clocks arise as a new paradigm to reduce the margins without sacrificing robustness. Their cycle-by-cycle adaptation to static and dynamic variability enables the use of reduced margins that only need to cover the differential variability of the circuit delays with regard to the elastic period. Given the substantial spatio-temporal correlation within every die, a significant reduction in the margins required to cover process variability, voltage and temperature fluctuations and aging can be achieved.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117118355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Progress and challenges of tungsten-filled through-silicon via 填钨硅通孔的研究进展与挑战
2010 IEEE International Conference on Integrated Circuit Design and Technology Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510274
D. Triyoso, T. Dao, T. Kropewnicki, F. Martínez, R. Noble, M. Hamilton
{"title":"Progress and challenges of tungsten-filled through-silicon via","authors":"D. Triyoso, T. Dao, T. Kropewnicki, F. Martínez, R. Noble, M. Hamilton","doi":"10.1109/ICICDT.2010.5510274","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510274","url":null,"abstract":"Through Silicon Via (TSV) has been used for back-end packaging and more recently, for front end active device integration. In this work we report recent progress and challenges for via cleaning, via filling and wafer bow / stress monitoring. Furthermore, the importance of preparation technique for accurate characterization of tungsten-filled TSV profile will be presented.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129476306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Simplified parameter extraction method for modeling on-chip spiral inductors 片上螺旋电感器建模的简化参数提取方法
2010 IEEE International Conference on Integrated Circuit Design and Technology Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510247
E. L. Tan, W. Koh
{"title":"Simplified parameter extraction method for modeling on-chip spiral inductors","authors":"E. L. Tan, W. Koh","doi":"10.1109/ICICDT.2010.5510247","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510247","url":null,"abstract":"This paper presents a simplified parameter extraction method for modeling on-chip spiral inductors. Our method bypasses time-consuming numerical optimization and is simpler than previous parameter extraction procedure. The parameters of the spiral inductor model can be extracted simply and directly without involving complicated formulas. It is also found that the extracted parameters are more accurate especially in the substrate lateral coupling elements. The extracted model shows excellent agreement between simulation and measurement over the frequency range of interest. With its simplicity and accuracy, the simplified parameter extraction method herein will find usefulness in the modeling and design of spiral inductors for radio frequency integrated circuits.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129881586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A GPU/CUDA implementation of the collection-diffusion model to compute SER of large area and complex circuits 一种用于计算大面积复杂电路SER的采集-扩散模型的GPU/CUDA实现
2010 IEEE International Conference on Integrated Circuit Design and Technology Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510293
J. Autran, S. Uznanski, S. Martinie, P. Roche, G. Gasiot, D. Munteanu
{"title":"A GPU/CUDA implementation of the collection-diffusion model to compute SER of large area and complex circuits","authors":"J. Autran, S. Uznanski, S. Martinie, P. Roche, G. Gasiot, D. Munteanu","doi":"10.1109/ICICDT.2010.5510293","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510293","url":null,"abstract":"This work reports the CUDA implementation of the collection-diffusion model to compute the soft-error rate (SER) of large area and/or complex circuits on graphics processing units (GPU). We detail the time parallelization introduced in the algorithm to accelerate by one order of magnitude the SER calculation. Code performances are evaluated on a NVIDIA Tesla C1060 GPU card for the calculation of the SER of a 65nm SRAM circuit subjected to an alpha-particle source irradiation.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121584310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Overlay-aware interconnect yield modeling in double patterning lithography 双图版光刻中覆盖感知互连良率建模
2010 IEEE International Conference on Integrated Circuit Design and Technology Pub Date : 2010-06-02 DOI: 10.1109/ICICDT.2010.5510275
Minoo Mirsaeedi, M. Anis
{"title":"Overlay-aware interconnect yield modeling in double patterning lithography","authors":"Minoo Mirsaeedi, M. Anis","doi":"10.1109/ICICDT.2010.5510275","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510275","url":null,"abstract":"In double patterning lithography, overlay error between two patterning steps at the same layer results in critical dimensions variability. In order to optimize the yield loss due to overlay error, statistical design techniques should be applied since overlay error is segueing from a systematic error into a random one for technology nodes smaller than 45-nm. In this paper, the effects of overlay error on interconnect layers are studied and the interconnect yield in presence of overlay error is modeled. Next, a yield optimization method is proposed to improve the parametric and functional yields of interconnect layers. Experimental results show that parametric yield loss is more problematic in negativetone DPL. Moreover, we show that different DFM techniques such as wire spreading are necessary to reach design constraints.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126064485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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