E. Ibe, K. Shimbo, Tadanobu Toba, Yoshio Taniguchi, H. Taniguchi
{"title":"Novel SER standards: Backgrounds and methodologies","authors":"E. Ibe, K. Shimbo, Tadanobu Toba, Yoshio Taniguchi, H. Taniguchi","doi":"10.1109/ICICDT.2010.5510259","DOIUrl":null,"url":null,"abstract":"Standard methods to quantify SER susceptibility in memory devices have been established during 2000–2008. JESD89A issued in 2006 covers a wide variety of test methods for terrestrial neutrons and alpha particles. Spallation and (quasi-) monoenergetic neutron tests are among the best options for the SER tests. The methods, however, are being recognized as getting more inaccurate as device scaling proceeds. SER in logic devices is also getting more serious so that standard testing methods have to be established for logic devices. The new standards may include strategies for mitigation of SERs as well. The backgrounds and methodologies to promote new SER standards for device, chip, board layers are discussed in the present paper.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Conference on Integrated Circuit Design and Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICDT.2010.5510259","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
Standard methods to quantify SER susceptibility in memory devices have been established during 2000–2008. JESD89A issued in 2006 covers a wide variety of test methods for terrestrial neutrons and alpha particles. Spallation and (quasi-) monoenergetic neutron tests are among the best options for the SER tests. The methods, however, are being recognized as getting more inaccurate as device scaling proceeds. SER in logic devices is also getting more serious so that standard testing methods have to be established for logic devices. The new standards may include strategies for mitigation of SERs as well. The backgrounds and methodologies to promote new SER standards for device, chip, board layers are discussed in the present paper.