Overlay-aware interconnect yield modeling in double patterning lithography

Abstract

In double patterning lithography, overlay error between two patterning steps at the same layer results in critical dimensions variability. In order to optimize the yield loss due to overlay error, statistical design techniques should be applied since overlay error is segueing from a systematic error into a random one for technology nodes smaller than 45-nm. In this paper, the effects of overlay error on interconnect layers are studied and the interconnect yield in presence of overlay error is modeled. Next, a yield optimization method is proposed to improve the parametric and functional yields of interconnect layers. Experimental results show that parametric yield loss is more problematic in negativetone DPL. Moreover, we show that different DFM techniques such as wire spreading are necessary to reach design constraints.