Through-Silicon-Via stress 3D modeling and design

Abstract

Through-Silicon-Via (TSV) processing is critical to 3D chip stacked integrated circuit (IC) technology. The understanding and management of the induced stresses in silicon due to coefficient of thermal expansion (CTE) mismatch is critical for the successful implementation of this process in circuit design and production. Most TSVs in these applications are copper (Cu) filled. Analysis of Cu-filled TSV induced stress has been reported by Okoro et. al [1], and the proposed stress measurement and model has been reported by Chidambaram et. al. [2].