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2021 18th International SoC Design Conference (ISOCC)最新文献

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High speed Continuous-time Delta Sigma Modulators for Wide-band Applications: A review paper 宽带应用的高速连续时间δ σ调制器:综述
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613952
Ankesh Jain
{"title":"High speed Continuous-time Delta Sigma Modulators for Wide-band Applications: A review paper","authors":"Ankesh Jain","doi":"10.1109/ISOCC53507.2021.9613952","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613952","url":null,"abstract":"This paper presents a review of high speed continuous time delta sigma modulators (CTDSM) designed for wideband applications. It analyzes different trade-offs involved in its design and choices available at architectural level suggesting the recipe for optimized design of wideband CTDSMs. It also discusses various design techniques used in the design of wideband CTDSMs and compares the performance of state-of-the-art wideband CTDSMs. This paper can serve as a starting point for the design of a low power wideband CTDSM.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129492457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Wideband Operational Trans-Conductance Amplifier with Feed-Forward Compensation Technique 采用前馈补偿技术的宽带运算跨导放大器
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613868
Muhammad Fakhri Mauludin, Dong-Ho Lee, Jusung Kim
{"title":"Wideband Operational Trans-Conductance Amplifier with Feed-Forward Compensation Technique","authors":"Muhammad Fakhri Mauludin, Dong-Ho Lee, Jusung Kim","doi":"10.1109/ISOCC53507.2021.9613868","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613868","url":null,"abstract":"This paper presents the design of two stage operational trans-conductance amplifier (OTA) with feed-forward compensation scheme. Without using Miller capacitance, proposed OTA presents a high gain and large bandwidth without compromising good phase margin. The prototype circuit is designed using TSMC 45nm process. Post layout simulation results show a 60.5 dB of gain, 546.6 MHz unity-gain frequency, and 73° phase margin while driving 8pF capacitive load and consuming 3.4 mW power from 1 V power supply.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122830076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-Complexity Voice Activity Detection Algorithm for Edge-Level Device 边缘级设备低复杂度语音活动检测算法
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9614000
Jin Hyun, Seungsik Moon, Youngjoo Lee
{"title":"Low-Complexity Voice Activity Detection Algorithm for Edge-Level Device","authors":"Jin Hyun, Seungsik Moon, Youngjoo Lee","doi":"10.1109/ISOCC53507.2021.9614000","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9614000","url":null,"abstract":"This paper presents two optimization techniques to relieve the computational complexity of the neural network based voice activity detection (VAD) task. Proposed techniques analyze the similarity between speech features by comparing the vectors at adjacent time steps and reduce the required computational cost by modifying internal elements based on the similarity. As a case study, a simple convolutional neural network for VAD was simulated with the proposed optimization techniques under the noisy environment, and experimental results show that the proposed techniques can reduce the required computational cost up to 33.6% with negligible performance degradation.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117149259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of 66.5dB IRR Baseband Analog with Filter Tuning 带滤波器调谐的66.5dB IRR基带模拟电路设计
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613855
Ji Hoon Song, Kangyoon Lee
{"title":"Design of 66.5dB IRR Baseband Analog with Filter Tuning","authors":"Ji Hoon Song, Kangyoon Lee","doi":"10.1109/ISOCC53507.2021.9613855","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613855","url":null,"abstract":"This paper introduces a design of baseband analog with high performance IRR (Image Rejection Ratio) to using wide-bandwidth for DSRC (Dedicated Short Range Communication) transceiver. In addition, an automatic filter tuning system has applied to in this circuit for higher PVT tolerance and accuracy of bandwidth. To reduce adjacent interferers and image signal in baseband circuit, Complex Band Pass Filter (BPF) is used in this system. Baseband analog has high performance of IRR 66.5 dB at 3-dB bandwidth and the Intermediate Frequency (IF) are 10MHz. This circuit is designed in 130nm CMOS process. Power consumption is 7.46mW under 1.2V power supply.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131563132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Early HW/SW Co-Verification Using Virtual Platforms 使用虚拟平台的早期软硬件协同验证
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613958
Jungyun Choi, K. Kang, Byunghoon Lee, Sangho Park, Jaewoo Im
{"title":"Early HW/SW Co-Verification Using Virtual Platforms","authors":"Jungyun Choi, K. Kang, Byunghoon Lee, Sangho Park, Jaewoo Im","doi":"10.1109/ISOCC53507.2021.9613958","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613958","url":null,"abstract":"Early HW/SW co-verification is important to minimize the product time-to-market. In this paper, a new VP (virtual platform) technique is introduced where two heterogeneous simulators, i.e., SystemC and RTL, communicate with each other through IPC (Inter Process Communication). Experimental results show how the proposed approach contributes to shorten VP debugging TAT (turn-around time) and shift-left HW/SW co-verification before FPGA is available. In addition, the proposed method shows a reduction in a setup time for a new platform where VP and HW emulator are combined to accelerate the simulation speed.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130680522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Estimation Method for Controlling Unstable Periodic Orbit Without Using Poincaré Map 一种不使用庞卡罗图控制不稳定周期轨道的估计方法
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613850
S. Aoki, T. Kousaka, Shota Uchino, Daiki Hozumi, H. Asahara
{"title":"An Estimation Method for Controlling Unstable Periodic Orbit Without Using Poincaré Map","authors":"S. Aoki, T. Kousaka, Shota Uchino, Daiki Hozumi, H. Asahara","doi":"10.1109/ISOCC53507.2021.9613850","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613850","url":null,"abstract":"A method for estimating unstable periodic orbits in switched dynamical system is proposed. The proposed method consists of a simple algorithm that does not require numerical calculations such as the Newton method. The proposed method is explained using a switched dynamical system that simulates the switching operation of a current-controlled DC-DC converter as an example, and an application example is shown based on numerical simulation results.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127224819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-speed StrongARM-latch-based Bang-bang Phase Detector in 40-nm CMOS Technology 基于40纳米CMOS技术的高速strongarm锁存器Bang-bang鉴相器
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613931
Gaeryun Sung, Jaeduk Han
{"title":"High-speed StrongARM-latch-based Bang-bang Phase Detector in 40-nm CMOS Technology","authors":"Gaeryun Sung, Jaeduk Han","doi":"10.1109/ISOCC53507.2021.9613931","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613931","url":null,"abstract":"This paper presents a high-speed strongARM-latch-based bang-bang phase detector (PD). Instead of using D-flipflops (DFF) or D-latches, which are used in conventional bang-bang PDs, strongARM latches are used to achieve high sensitivity owing to their regeneration behaviors. By comparing the clock-to-Q delay(tcq) and maximum data rate of conventional and proposed phase detectors, it is found that the proposed strongARM-latch -based bang-bang PD has a smaller clock-to-Q delay and a higher data rate.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122907220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
PSO-based Design Procedure for Class-DE Inverter 基于pso的de类逆变器设计程序
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613924
Wenqi Zhu, Yutaro Komiyama, Kien Nguyan, H. Sekiya
{"title":"PSO-based Design Procedure for Class-DE Inverter","authors":"Wenqi Zhu, Yutaro Komiyama, Kien Nguyan, H. Sekiya","doi":"10.1109/ISOCC53507.2021.9613924","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613924","url":null,"abstract":"In this research, a novel numerical design strategy is presented for the class-DE inverter design, which is based on particle swarm optimization (PSO) algorithm. Compared with previous numerical design methods based on Newton’s method, the proposed method shows convenience without restricting the number of design parameters. Additionally, no initial estimation is needed for ensuring convergence. Therefore, system-level optimization, which considers optimized inductor designs, can be realized. A design example of the class-DE inverter is shown in this paper. The numerical calculation proved the validity of the proposed design method.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128151953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Background Timing-Skew Mismatch Calibration for Time-Interleaved ADCs 时间交错adc的背景时偏失配校准
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613935
Mingqiang Guo, Sai-Weng Sin, R. Martins
{"title":"Background Timing-Skew Mismatch Calibration for Time-Interleaved ADCs","authors":"Mingqiang Guo, Sai-Weng Sin, R. Martins","doi":"10.1109/ISOCC53507.2021.9613935","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613935","url":null,"abstract":"Time-interleaved ADC is widely used in high-speed applications. This structure can increase the effective sampling rate of the entire converter by multiplexing multiple ADCs in parallel. However, this architecture will be affected by mismatches between different sub-converters, including offset, gain, and timing. Timing skew will produce dynamic errors, thus posing a greater challenge. This paper presents recent state-of-the-art solutions addressing the timing skew mismatch in TI ADC through two types of background blind calibration techniques: a) methods based on deterministic equalization and b) techniques based on statistical information of the input signal.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128158256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Hybrid Test Access Mechanism for Multiple Identical Cores 多个相同核的混合测试访问机制
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613908
Sangjun Lee, Jongho Park, Inhwan Lee, Kwonhyoung Lee, Sungho Kang
{"title":"Hybrid Test Access Mechanism for Multiple Identical Cores","authors":"Sangjun Lee, Jongho Park, Inhwan Lee, Kwonhyoung Lee, Sungho Kang","doi":"10.1109/ISOCC53507.2021.9613908","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613908","url":null,"abstract":"Recently, the demand for artificial intelligence such as IoT, autonomous vehicles and cloud is rapidly increased, and intelligent processors are expected to be used in all objects such as home appliances and automobiles. Intelligent processors are composed of multiple identical cores for parallel computation and acceleration of neural networks to implement artificial intelligence services. Due to the high degree of integration and the increase of test complexity in intelligent processors, efficient parallel testing is required. In this paper, a new test access mechanism is proposed to test the multiple identical cores. The proposed method solves the problem of the previous parallel test access mechanism in low-yield system without additional hardware and can test multiple identical cores at the cost of testing one core.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"13 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114123870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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