{"title":"基于40纳米CMOS技术的高速strongarm锁存器Bang-bang鉴相器","authors":"Gaeryun Sung, Jaeduk Han","doi":"10.1109/ISOCC53507.2021.9613931","DOIUrl":null,"url":null,"abstract":"This paper presents a high-speed strongARM-latch-based bang-bang phase detector (PD). Instead of using D-flipflops (DFF) or D-latches, which are used in conventional bang-bang PDs, strongARM latches are used to achieve high sensitivity owing to their regeneration behaviors. By comparing the clock-to-Q delay(tcq) and maximum data rate of conventional and proposed phase detectors, it is found that the proposed strongARM-latch -based bang-bang PD has a smaller clock-to-Q delay and a higher data rate.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"High-speed StrongARM-latch-based Bang-bang Phase Detector in 40-nm CMOS Technology\",\"authors\":\"Gaeryun Sung, Jaeduk Han\",\"doi\":\"10.1109/ISOCC53507.2021.9613931\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a high-speed strongARM-latch-based bang-bang phase detector (PD). Instead of using D-flipflops (DFF) or D-latches, which are used in conventional bang-bang PDs, strongARM latches are used to achieve high sensitivity owing to their regeneration behaviors. By comparing the clock-to-Q delay(tcq) and maximum data rate of conventional and proposed phase detectors, it is found that the proposed strongARM-latch -based bang-bang PD has a smaller clock-to-Q delay and a higher data rate.\",\"PeriodicalId\":185992,\"journal\":{\"name\":\"2021 18th International SoC Design Conference (ISOCC)\",\"volume\":\"138 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-10-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 18th International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC53507.2021.9613931\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 18th International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC53507.2021.9613931","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High-speed StrongARM-latch-based Bang-bang Phase Detector in 40-nm CMOS Technology
This paper presents a high-speed strongARM-latch-based bang-bang phase detector (PD). Instead of using D-flipflops (DFF) or D-latches, which are used in conventional bang-bang PDs, strongARM latches are used to achieve high sensitivity owing to their regeneration behaviors. By comparing the clock-to-Q delay(tcq) and maximum data rate of conventional and proposed phase detectors, it is found that the proposed strongARM-latch -based bang-bang PD has a smaller clock-to-Q delay and a higher data rate.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
