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2021 18th International SoC Design Conference (ISOCC)最新文献

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Resistive Degeneration Linearization Dynamic Residue Amplifiers for Pipelined ADCs 用于流水线adc的电阻退化线性化动态残差放大器
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613883
Ziwei Li, Guoyao Wu, Yutong Zhao, Fan Ye, Junyan Ren
{"title":"Resistive Degeneration Linearization Dynamic Residue Amplifiers for Pipelined ADCs","authors":"Ziwei Li, Guoyao Wu, Yutong Zhao, Fan Ye, Junyan Ren","doi":"10.1109/ISOCC53507.2021.9613883","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613883","url":null,"abstract":"Residue amplifier is a crucial part of a pipelined ADC design. The linearity of the residue amplifier directly affects the linearity of the pipelined ADC. This paper introduces the resistive degeneration linearization technique into dynamic residue amplifier designs. Both NMOS and CMOS dynamic amplifiers are implemented and simulated with a 28nm CMOS technology at 100MS/s. The simulation results show over -77dB THD for both dynamic amplifiers with large output swings after a foreground calibration.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"17 20","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120821046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Fast Locking All Digital Delay Locked Loop with wide operating frequency ranged from 0.5 GHz to 1.8 GHz in 40nm Process 40nm工艺下工作频率为0.5 GHz ~ 1.8 GHz的快速锁定全数字延迟锁相环
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613874
Ko-Chi Kuo
{"title":"A Fast Locking All Digital Delay Locked Loop with wide operating frequency ranged from 0.5 GHz to 1.8 GHz in 40nm Process","authors":"Ko-Chi Kuo","doi":"10.1109/ISOCC53507.2021.9613874","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613874","url":null,"abstract":"The all-digital delay locked loop is proposed with a 10-bit hybrid successive approximation register control circuit, a control unit, and a digital delay line to achieve the fast locking of DLL. The input frequency is processed by the hybrid successive approximation register control circuit. By controlling the digital delay line, the locking operation of DLL can be accomplished through the binary weighted searching algorithm by the successive approximation register. The digital delay line uses two sets of relative delay line methods to increase the allowable operating range of the circuit. An improved parallel NAND element is implemented to reduce jitters. A thermometer code is adopted in the fine tuning delay line in order to improve the linearity and hence the reduced jitters. The improved hybrid successive approximation register is implemented to achieve a better tolerance to the environmental variations and can continue to tracking after DLL have being locked. The simulated locked range of the proposed design is from 0.5 GHz to 1.8 GHz with supply voltage of 0.9V. The proposed design can be locked in 18 clock cycles and implemented in TSMC 40nm process.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124871921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Voltage-Controlled Magnetic Anisotropy based True Random Number Generator 基于压控磁各向异性的真随机数发生器
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613854
Lawrence Roman A. Quizon, A. Alvarez, Christoper G. Santos, M. Rosales, J. Hizon, Maria Patricia Rouelli G. Sabino
{"title":"A Voltage-Controlled Magnetic Anisotropy based True Random Number Generator","authors":"Lawrence Roman A. Quizon, A. Alvarez, Christoper G. Santos, M. Rosales, J. Hizon, Maria Patricia Rouelli G. Sabino","doi":"10.1109/ISOCC53507.2021.9613854","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613854","url":null,"abstract":"An emerging nanodevice called voltage controlled magnetic anisotropy magnetic tunnel junction (VCMA-MTJ) exhibits stochastic behavior that can be taken advantage of to produce random numbers at low power, low area, and high speed. In this paper, a 40MHz 104fJ/bit true random number generator (tRNG) was designed that works by applying 1V pulses to the VCMA-MTJ and then reading the resultant state, achieving 6800x the throughput of the most energy-efficient MTJ-based tRNG module designed for security while only consuming 5.21x more energy per bit. However, VCMA-MTJ based tRNG was also found to be very sensitive to variations in free-layer thickness, which can be solved by trading off an 8x increase in area and energy consumption.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"331 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123324295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Design of Low-Power Bootstrapped CMOS Switch for 20MS/s 12-bit Charge Sharing SAR ADCs 用于20MS/s 12位电荷共享SAR adc的低功耗自启动CMOS开关设计
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613861
Jung-Hyun Lee, Kangyoon Lee
{"title":"A Design of Low-Power Bootstrapped CMOS Switch for 20MS/s 12-bit Charge Sharing SAR ADCs","authors":"Jung-Hyun Lee, Kangyoon Lee","doi":"10.1109/ISOCC53507.2021.9613861","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613861","url":null,"abstract":"This paper presents the design and implementation of a low-power bootstrapped CMOS switch composed of a 12-bit charge sharing analog-to-digital converter(ADC) for ultrasound diagnostic medical devices. The proposed charge sharing ADC architecture consists of unit capacitor array and switches with low threshold voltage devices to minimize the size of the ADC. As the bootstrapped switch structure is employed, the switch on-resistance is constant regardless of the input voltage swings. It leads to a reduction in the third harmonic distortion caused by on-resistance of the switches. Thus, the proposed ADC with the bootstrapped switches had ENOB of 10.64-bit and SNDR of 65.82dB at the 5MHz input frequency. The designed ADC had the size of 1600um x 505um with 130nm CMOS process.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123467363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficient Signal Processing Acceleration using OpenCL-based FPGA-GPU Hybrid Cooperation for Reconfigurable ECG Diagnosis 利用基于opencl的FPGA-GPU混合协作实现可重构心电诊断的高效信号处理加速
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613894
Dongkyu Lee, Seungmin Lee, Daejin Park
{"title":"Efficient Signal Processing Acceleration using OpenCL-based FPGA-GPU Hybrid Cooperation for Reconfigurable ECG Diagnosis","authors":"Dongkyu Lee, Seungmin Lee, Daejin Park","doi":"10.1109/ISOCC53507.2021.9613894","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613894","url":null,"abstract":"With the development of Internet of things (IoT), where humans and machines interact, healthcare that measures and diagnoses bio-signals is advancing. The electrocardiogram (ECG) signal has different normal beat characteristics for each person, and it requires long-term data for detecting abnormalities. In this paper, we increased the detection rate of the normal signals by learning the reference signal, which is the standard for diagnosing ECG signals, as individual-specific signals from existing fixed data. In addition, we proposed an OpenCL-based FPGA-GPU hybrid cooperative platform to efficiently diagnose long-term, large-capacity ECG signals.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125556489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Effective Spare Allocation Methodology for 3D Memory Repair with BIRA 一种有效的BIRA三维记忆修复备件分配方法
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613980
Seung Ho Shin, Hayoung Lee, Younwoo Yoo, Sungho Kang
{"title":"An Effective Spare Allocation Methodology for 3D Memory Repair with BIRA","authors":"Seung Ho Shin, Hayoung Lee, Younwoo Yoo, Sungho Kang","doi":"10.1109/ISOCC53507.2021.9613980","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613980","url":null,"abstract":"Three-dimensional (3D) memory is widely developed to fulfill the ever-increasing memory densities. For the high reliability of 3D memory, the traditional spare structures that consist of simple rows and columns have a difficulty to maximize the efficiency of spare allocation. Therefore, various spare structures are adopted to achieve a high repair rate improvement for multiple banks memory. However, the previous studies have not proposed any methodology to allocate various spare structures with BIRA. For this reason, a new effective spare allocation methodology for the pre-bond and the post-bond repair is proposed. Also, the methodology can be verified by six representative various spare structures with the sequential allocation BIRA.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"517 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116231963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Continuous-time Delta-Sigma Modulators: Single-loop versus MASH 连续时间δ - σ调制器:单回路与MASH
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613910
Liang Qi, Tianming Ni, Xinyu Qin, Mingyi Chen, Yongfu Li, Guoxing Wang
{"title":"Continuous-time Delta-Sigma Modulators: Single-loop versus MASH","authors":"Liang Qi, Tianming Ni, Xinyu Qin, Mingyi Chen, Yongfu Li, Guoxing Wang","doi":"10.1109/ISOCC53507.2021.9613910","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613910","url":null,"abstract":"Oversampled continuous-time (CT) Delta-Sigma modulators (DSM) have been continued to increase the maximum clock rate, thus extending the achievable signal bandwidth. This development is the result of advanced CMOS technologies and innovative ways to employ this technology. On the other hand, single-loop (SL) and multi-stage noise-shaping (MASH) are two essential architectures for the implementation of CT DSMs. This paper outlined advanced SL and MASH improvements for CT DSMs and compared both of them.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114471765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A High Speed OOK Modulator at 300 GHz using LO Cancellation Technique 一种采用本路对消技术的300 GHz高速OOK调制器
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613853
Zubair Mehmood, M. Seo
{"title":"A High Speed OOK Modulator at 300 GHz using LO Cancellation Technique","authors":"Zubair Mehmood, M. Seo","doi":"10.1109/ISOCC53507.2021.9613853","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613853","url":null,"abstract":"This paper presents a high speed On-Off Keying (OOK) modulator for future terahertz communication using local oscillator (LO) cancellation technique. Post layout full-wave EM simulation results are performed up to 25 Gbps data-rate. The circuit is implemented in 250nm InP HBT technology. The modulator output at OFF position is 30% to its output at ON position. The proposed modulator design consumes power up to 53 mW and occupies active chip area of 0.01 mm2.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124544713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
PPG Sensors for The New Normal: A Review 新常态下的PPG传感器:综述
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613962
Qiuyang Lin, Nick Van Helleptte
{"title":"PPG Sensors for The New Normal: A Review","authors":"Qiuyang Lin, Nick Van Helleptte","doi":"10.1109/ISOCC53507.2021.9613962","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613962","url":null,"abstract":"Monitoring health parameters via wearables is rapidly gaining popularity. As part of wearable technology, optical Photoplethysmogram (PPG) has attracted considerable consumer interest. While PPG is traditionally used on the finger or on the wrist, thanks to advancements in miniaturization, improved power consumption and dynamic range, it uses more and more at other locations like on the chest and in the ear. Thus, rather than monitoring heart rate and blood saturation level, other biomedical signals such as the respiration rate and the glucose level can be extracted. These parameters might be helpful to monitor the health status or diagnose covid patients during the new normal. This paper reviews two state-of-the-art PPG sensor interfaces. The future development trends are provided as well.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125107671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Ability to generate output series for Hysteresis Reservoir Computing 能够为迟滞油藏计算生成输出序列
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9614006
Tsukasa Saito, K. Jin'no
{"title":"Ability to generate output series for Hysteresis Reservoir Computing","authors":"Tsukasa Saito, K. Jin'no","doi":"10.1109/ISOCC53507.2021.9614006","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9614006","url":null,"abstract":"Hysteresis reservoir computing generates a variety of output series by changing the parameters of the elements. In this paper, we show that hysteresis reservoir computing has improved its learning ability by changing the parameters, and can represent specific series data.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114345687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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