Ziwei Li, Guoyao Wu, Yutong Zhao, Fan Ye, Junyan Ren
{"title":"用于流水线adc的电阻退化线性化动态残差放大器","authors":"Ziwei Li, Guoyao Wu, Yutong Zhao, Fan Ye, Junyan Ren","doi":"10.1109/ISOCC53507.2021.9613883","DOIUrl":null,"url":null,"abstract":"Residue amplifier is a crucial part of a pipelined ADC design. The linearity of the residue amplifier directly affects the linearity of the pipelined ADC. This paper introduces the resistive degeneration linearization technique into dynamic residue amplifier designs. Both NMOS and CMOS dynamic amplifiers are implemented and simulated with a 28nm CMOS technology at 100MS/s. The simulation results show over -77dB THD for both dynamic amplifiers with large output swings after a foreground calibration.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"17 20","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Resistive Degeneration Linearization Dynamic Residue Amplifiers for Pipelined ADCs\",\"authors\":\"Ziwei Li, Guoyao Wu, Yutong Zhao, Fan Ye, Junyan Ren\",\"doi\":\"10.1109/ISOCC53507.2021.9613883\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Residue amplifier is a crucial part of a pipelined ADC design. The linearity of the residue amplifier directly affects the linearity of the pipelined ADC. This paper introduces the resistive degeneration linearization technique into dynamic residue amplifier designs. Both NMOS and CMOS dynamic amplifiers are implemented and simulated with a 28nm CMOS technology at 100MS/s. The simulation results show over -77dB THD for both dynamic amplifiers with large output swings after a foreground calibration.\",\"PeriodicalId\":185992,\"journal\":{\"name\":\"2021 18th International SoC Design Conference (ISOCC)\",\"volume\":\"17 20\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-10-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 18th International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC53507.2021.9613883\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 18th International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC53507.2021.9613883","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Resistive Degeneration Linearization Dynamic Residue Amplifiers for Pipelined ADCs
Residue amplifier is a crucial part of a pipelined ADC design. The linearity of the residue amplifier directly affects the linearity of the pipelined ADC. This paper introduces the resistive degeneration linearization technique into dynamic residue amplifier designs. Both NMOS and CMOS dynamic amplifiers are implemented and simulated with a 28nm CMOS technology at 100MS/s. The simulation results show over -77dB THD for both dynamic amplifiers with large output swings after a foreground calibration.