A Fast Locking All Digital Delay Locked Loop with wide operating frequency ranged from 0.5 GHz to 1.8 GHz in 40nm Process

Abstract

The all-digital delay locked loop is proposed with a 10-bit hybrid successive approximation register control circuit, a control unit, and a digital delay line to achieve the fast locking of DLL. The input frequency is processed by the hybrid successive approximation register control circuit. By controlling the digital delay line, the locking operation of DLL can be accomplished through the binary weighted searching algorithm by the successive approximation register. The digital delay line uses two sets of relative delay line methods to increase the allowable operating range of the circuit. An improved parallel NAND element is implemented to reduce jitters. A thermometer code is adopted in the fine tuning delay line in order to improve the linearity and hence the reduced jitters. The improved hybrid successive approximation register is implemented to achieve a better tolerance to the environmental variations and can continue to tracking after DLL have being locked. The simulated locked range of the proposed design is from 0.5 GHz to 1.8 GHz with supply voltage of 0.9V. The proposed design can be locked in 18 clock cycles and implemented in TSMC 40nm process.