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A CMOS Power Management Unit with Undervoltage Lockout Circuit as Startup for Piezoelectric Energy Harvesting Applications 具有欠压锁止电路的CMOS电源管理单元用于压电能量收集应用
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613995
S. L. Mindoro, John Owen Cabuyadao, Arcel G. Leynes, Maria Sophia Ralota, Zyrel Renzo Sanchez, J. Hizon, M. Rosales, M. T. D. Leon
{"title":"A CMOS Power Management Unit with Undervoltage Lockout Circuit as Startup for Piezoelectric Energy Harvesting Applications","authors":"S. L. Mindoro, John Owen Cabuyadao, Arcel G. Leynes, Maria Sophia Ralota, Zyrel Renzo Sanchez, J. Hizon, M. Rosales, M. T. D. Leon","doi":"10.1109/ISOCC53507.2021.9613995","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613995","url":null,"abstract":"This paper presents an integrated and self-starting power management unit (PMU) for piezoelectric energy harvesters. The system utilizes an undervoltage lockout (UVLO) circuit with an active voltage doubler, Dickson charge pump, and low dropout regulator. The UVLO circuit allows intermittent charging of storage capacitors to their target voltages during an undervoltage condition, resulting in improved self-startup capabilities and reduced power dissipation at startup. Implemented using AMS 0.35-µm CMOS process, the system is able to achieve a regulated 3.3 V DC voltage with 228 ms startup time using a 1 V AC voltage input with a frequency of 102 Hz.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114632137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2-GHz Reconfigurable Transmitter Using A Class-D PA and A Multi-Tapped Transformer 使用d类PA和多抽头变压器的2 ghz可重构发射机
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613956
Reza E. Rad, S. Choi, Sungjin Kim, B. S. Rikan, Kangyoon Lee
{"title":"A 2-GHz Reconfigurable Transmitter Using A Class-D PA and A Multi-Tapped Transformer","authors":"Reza E. Rad, S. Choi, Sungjin Kim, B. S. Rikan, Kangyoon Lee","doi":"10.1109/ISOCC53507.2021.9613956","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613956","url":null,"abstract":"This paper presents a 2-GHz reconfigurable transmitter designed for the high-bands uplink of an NB-IoT RF transceiver. The transmitter is formed by an active upconversion mixer, a fully differential class D Power Amplifier (PA). To do the coarse power gain reconfiguration of the TX a multi-tapped transformer is designed which offers multi secondary taps delivering various levels of power to the antenna. To do a fine-tuning of the output power level a capacitor bank is implemented at the primary side of the transformer. The capacitor bank is tuning the resonance frequency while is forming an LC tank with the primary side. The proposed TX is designed in an RF 65-nm CMOS technology. The output power is delivered to another external PA through an off-chip matching network. The designs deliver a reconfigurable output between 2 dBm to 10 dBm while it is receiving an IF signal with 0 dBm power. The TX consumes 60 mA current through a 3V VDD.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114706173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
CNN Accelerator with Minimal On-Chip Memory Based on Hierarchical Array 基于分层阵列的最小片上存储器CNN加速器
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613997
Hyun-Wook Son, YongSeok Na, TaeHyun Kim, Ali A. Al-Hamid, Hyungwon Kim
{"title":"CNN Accelerator with Minimal On-Chip Memory Based on Hierarchical Array","authors":"Hyun-Wook Son, YongSeok Na, TaeHyun Kim, Ali A. Al-Hamid, Hyungwon Kim","doi":"10.1109/ISOCC53507.2021.9613997","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613997","url":null,"abstract":"This paper presents an architecture of CNN accelerator based on a new processing element (PE) array called a diagonal cyclic array. It can significantly reduce the burden of repeated memory accesses for feature data and weight parameters for CNN models. To evaluate the effectiveness of the proposed architecture, we implemented a CNN accelerator for YOLOv4-Tiny consisting of 9 layers. We also present how to optimize the local buffer size with little sacrifice of inference speed. We evaluated the example CNN accelerator using FPGA implementation with 24932 LUTs, 584 DSP blocks and a on-chip memory of only 58KB. It demonstrates an accuracy 58% (mAP0.5) with computation time of 240ms for each input image using a clock speed of 100MHz. This speed is expected to reach 2.4ms using a clock speed of 1GHz, if implemented in a silicon SoC using a sub-micron process.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127940929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Review on Recent Development of Input Impedance Boosting for Bio-Potential Amplifiers 生物电位放大器输入阻抗增强研究进展综述
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613951
Shuang Song, Yizhao Zhou, Mengyu Li, Menglian Zhao
{"title":"A Review on Recent Development of Input Impedance Boosting for Bio-Potential Amplifiers","authors":"Shuang Song, Yizhao Zhou, Mengyu Li, Menglian Zhao","doi":"10.1109/ISOCC53507.2021.9613951","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613951","url":null,"abstract":"Bio-potential signals like Electrocardiogram(ECG) and Electroencephalogram(EEG) are recorded routinely in modern clinical practice and daily life, providing helpful information for early diagnosis of disease. A very high input impedance (Zin) of the readout is crucial in emerging applications, e.g. drivers’ monitoring, embedded smart home heath monitoring. This paper gives a review on existing techniques including 1) positive feedback technique; 2) auxiliary path feedforward technique; 3) current feedback topology. This paper focuses on the development on each Zin boosting technique in recent years, like auxiliary capacitor assisted input buffer and current feedback topology with parasitic capacitance shielding of the input transistors, which help to achieve a reliable Gohm input impedance with minimum power consumption.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131803697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Configurable Butterfly Unit Architecture for NTT/INTT in Homomorphic Encryption 同态加密中NTT/INTT的可配置蝴蝶单元体系结构
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9614034
Phap Duong-Ngoc, T. Tan, Hanho Lee
{"title":"Configurable Butterfly Unit Architecture for NTT/INTT in Homomorphic Encryption","authors":"Phap Duong-Ngoc, T. Tan, Hanho Lee","doi":"10.1109/ISOCC53507.2021.9614034","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9614034","url":null,"abstract":"This paper proposes a configurable architecture of butterfly unit (BU) supporting number theoretic transform (NTT) and inverse NTT (INTT) accelerators in the ring learning with error based homomorphic encryption. The proposed architecture is fully pipelined and carefully optimized the critical path delay. To compare with related works, several BU designs of different bit-size specific primes are synthesized and successfully placed-and-routed on the Xilinx Zynq UltraScale+ ZCU102 FPGA platform. Implementation results show that the proposed BU designs achieve 3× acceleration with more efficient resource utilization compared with previous works. Thus, the proposed BU architecture is worthwhile to develop NTTINTT accelerators in advanced homomorphic encryption systems.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133079519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
High Performance and Area Efficient Ferroelectric FET based Reconfigurable Logic Circuit 基于高效率铁电场效应晶体管的可重构逻辑电路
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613886
Dong Han Ko, Sehee Lim, Young Kyu Lee, Seong-ook Jung
{"title":"High Performance and Area Efficient Ferroelectric FET based Reconfigurable Logic Circuit","authors":"Dong Han Ko, Sehee Lim, Young Kyu Lee, Seong-ook Jung","doi":"10.1109/ISOCC53507.2021.9613886","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613886","url":null,"abstract":"The emerging nonvolatile memory (NVM)-based logic in-memory (LiM) structure can reduce power consumption caused by data transfer since it integrates memory and logic units very closely. The ferroelectric field-effect transistor (FeFET) is one of the promising candidates for NVM-based LiM structure owing to its unique characteristics: three-terminal structure and high ION/OFF ratio. In this paper, we propose the FeFET based reconfigurable logic circuit which can provide AND/OR/XOR logic value in a single circuit. Simulation results show that it can achieve a 67% lower transistor number, 17% faster delay, and 54% less energy than STT-MTJ based reconfigurable logic circuit.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132793333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Soft Error Sensitivity of Magnetic Random Access Memory and Its Radiation Hardening Design 磁随机存储器的软误差灵敏度及其辐射硬化设计
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613876
Bi Wang, Zhaohao Wang, Min Wang, Weisheng Zhao, Liang Wang, Yuanfu Zhao
{"title":"Soft Error Sensitivity of Magnetic Random Access Memory and Its Radiation Hardening Design","authors":"Bi Wang, Zhaohao Wang, Min Wang, Weisheng Zhao, Liang Wang, Yuanfu Zhao","doi":"10.1109/ISOCC53507.2021.9613876","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613876","url":null,"abstract":"Spin-orbit torque magnetic random access memory (SOT-MRAM) has been considered as a candidate for the next-generation memory thanks to its ultrafast switching speed, zero static power consumption, and nearly unlimited endurance. However, the pulse width of writing current in the SOT-MRAM is comparable to that of radiation-induced current in spatial environments. Especially, the SOT-MRAM consists of nano-scale devices and may suffer from soft errors induced by multiple-bit upset (MBU). In this paper, we analyze the sensitivity to soft errors of SOT-MRAM. Then we review the radiation hardening technologies of MRAM and summary the highlighted issues, which will contribute to the integration of MRAM into aerospace and avionics electronics in hostile environments.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131030046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices 基于高精度SRAM的AI边缘设备内存计算设计方法
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613913
Tianzhu Xiong, Yongliang Zhou, Yuyao Kong, Bo Wang, An Guo, Yufei Wang, Chen Xue, Haiming Hsu, Xin Si, Jun Yang
{"title":"Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices","authors":"Tianzhu Xiong, Yongliang Zhou, Yuyao Kong, Bo Wang, An Guo, Yufei Wang, Chen Xue, Haiming Hsu, Xin Si, Jun Yang","doi":"10.1109/ISOCC53507.2021.9613913","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613913","url":null,"abstract":"Artificial Intelligence (AI) processors commonly use deep-learning-based neural networks (DNN), which mainly include convolution layers and fully connected (FC) layers. Both the convolution and FC layers require highly parallel multiply-and-accumulate (MAC) operations and generate a great deal of intermediate data. Under the von Neumann computing architecture, data transfer between processor and memory imposes high energy consumption and long latency, which significantly deteriorates the system’s performance and efficiency. Computation-in-memory (CIM) is a promising candidate to improve the energy efficiency of multiply-and accumulate (MAC) operations of artificial intelligence (AI) chips. However, there are always constraints between high precision and high energy efficiency in CIM. This paper reviews the precision requirements of popular DNN models, and outlines the tradeoff between the precision and the energy efficiency in SRAM-CIM designs.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131403343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design of 100 GHz OOK Transceiver in 28nm CMOS Process for High Speed Communication 基于28nm CMOS工艺的100ghz OOK高速通信收发器设计
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613889
Zubair Mehmood, Waseem Abbas, M. Seo
{"title":"Design of 100 GHz OOK Transceiver in 28nm CMOS Process for High Speed Communication","authors":"Zubair Mehmood, Waseem Abbas, M. Seo","doi":"10.1109/ISOCC53507.2021.9613889","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613889","url":null,"abstract":"This paper presents a 100 GHz OOK based transceiver designed in 28nm CMOS process for future millimeter wave wireless communication networks. The transmitter includes a novel OOK modulator with 21.6 dB isolation. The power amplifier with 13 dB gain is designed to achieve EIRP of 5 dB. The distance between transmitter and receiver is 0.5 cm. The receiver includes the two-stage low noise amplifier and novel distributed demodulator with open drain output buffer. The chip area of transmitter and receiver with probing pads is 1.26 mm2 and 0.72 mm2 respectively.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115450531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 5.8 GHz RF-DC Based Energy-Harvesting Front-End with a Load-Lighting LC-Oscillator Based Voltage Booster for a SWIPT IC 用于SWIPT集成电路的5.8 GHz射频直流能量收集前端和负载照明lc振荡器电压升压器
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613923
Reza E. Rad, B. S. Rikan, Kangyoon Lee
{"title":"A 5.8 GHz RF-DC Based Energy-Harvesting Front-End with a Load-Lighting LC-Oscillator Based Voltage Booster for a SWIPT IC","authors":"Reza E. Rad, B. S. Rikan, Kangyoon Lee","doi":"10.1109/ISOCC53507.2021.9613923","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613923","url":null,"abstract":"This paper presents a novel approach to implement an Energy-Harvesting Front-End (EH-FE) based on a 5.8 GHz RF-DC converter and a light-loading LC-Oscillator (LCO) based Voltage Booster (VB) for a Simultaneous Wireless Information and Power Transfer (SWIPT) Integrated Circuit (IC) application. An RF-DC converter operating at 5.8 GHz as the frequency of the SWIPT IC forms the proposed EH-FE. The RF-DC is in series with a high sensitive LCO-VB introducing the Load-Lighting Effect (LLE) on the RF-DC’s loading condition to perform a proper voltage boosting as the novel approach for RF-DC based self-power ICs operating at multi-GHz frequency bands. The load lighting effect of the VB improves the effective loading for the RF-DC from 10.7 Ω to 3.7 kΩ based on the presented analysis. The proposed EH-FE boosts the 5.8 RF-DC’s output voltage to 5V due to the LLE when the antenna sees a signal with 0 dBm power.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114364473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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