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2021 18th International SoC Design Conference (ISOCC)最新文献

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Spatial Non-Maximum Suppression for Object Detection using Correlation and Dynamic Thresholds 基于相关性和动态阈值的空间非最大值抑制目标检测
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9614023
Xiangyu Zhang, Wenyan Su, Juan Li, Jingwei Li, Xin Lou
{"title":"Spatial Non-Maximum Suppression for Object Detection using Correlation and Dynamic Thresholds","authors":"Xiangyu Zhang, Wenyan Su, Juan Li, Jingwei Li, Xin Lou","doi":"10.1109/ISOCC53507.2021.9614023","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9614023","url":null,"abstract":"This paper presents a spatial-non-maximal suppression algorithm (SNMS) that is hardware friendly and improves efficiency. Unlike the greedy NMS, which merely focuses on the scores, the SNMS considers the correlation among the overlapped boxes and applies dynamic thresholds which are determined by the boxes density. Thus, the SNMS integrates spatial and contextual information with the scores. Three techniques are used to shorten the latency. First of all, the SNMS starts the suppression as soon as the 1st candidate box is ready. Secondly, the candidate boxes on different layers are analyzed in parallel. Thirdly, the representatives of boxes clusters (BC) which consist of overlapped boxes at multiply scales, are selected on the fly based on the forecastable position relationships. Experimental results demonstrate that the SNMS can compress the number of candidate boxes 30 times at maximum and maintains the accuracy at the same time.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114449549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 20-Gb/s Digitally Adaptive Linear Equalizer with 25dB loss for Single-ended Interfaces in 65nm CMOS 用于65nm CMOS单端接口的20gb /s、25dB损耗的数字自适应线性均衡器
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613998
Yunha Kang, Junyoung Song
{"title":"A 20-Gb/s Digitally Adaptive Linear Equalizer with 25dB loss for Single-ended Interfaces in 65nm CMOS","authors":"Yunha Kang, Junyoung Song","doi":"10.1109/ISOCC53507.2021.9613998","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613998","url":null,"abstract":"This paper describes the digitally adaptive linear equalizer with 25dB channel loss for single-ended interfaces in a 65nm CMOS technology. The proposed adaptation method achieves optimal-boosting using a comparator and digital logic. So, the proposed adaptation is insensitive to process variation. The adaptive linear equalizer is verified by post-layout simulations achieved 0.83 unit-interval (UI) eye-opening. The proposed adaptive linear equalizer occupies 0.08mm2, and power efficiency is 0.58pJ/b at 20Gb/s with 1.2V power supply.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114943468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-Complexity On-Device ECG Classifier using Binarized Neural Network 基于二值化神经网络的低复杂度设备心电分类器
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613942
S. Yoo, Seungwoo Hong, Youngjoo Lee
{"title":"Low-Complexity On-Device ECG Classifier using Binarized Neural Network","authors":"S. Yoo, Seungwoo Hong, Youngjoo Lee","doi":"10.1109/ISOCC53507.2021.9613942","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613942","url":null,"abstract":"Targeting the real-time arrhythmia diagnosis on resource-limited devices, in this paper, we present a cost-effective heartbeat classifier that uses a binarized neural network (BNN). Based on the previous CNN-based approaches, several optimization schemes are applied for error-resilient binarization. With the full-precision gradient descent, the proposed model reduces the variance during the training. The learnable activation function additionally compensates binarization errors by adjusting information shifts. Targeting the MIT-BIH arrhythmia database, allowing less than 1% accuracy drop, the proposed BNN model reduces the energy consumption and the memory usage by 94.63% and 84.62%, respectively, compared to the full-precision CNN-based model.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125868398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Intrinsic Capacitance based Multi bit Computing in Memory 基于本禀电容的存储器多比特计算
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613882
Young Kyu Lee, Minjune Yeo, Seokhee Cho, Seong-ook Jung
{"title":"Intrinsic Capacitance based Multi bit Computing in Memory","authors":"Young Kyu Lee, Minjune Yeo, Seokhee Cho, Seong-ook Jung","doi":"10.1109/ISOCC53507.2021.9613882","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613882","url":null,"abstract":"Computing in memory (CIM) technique is being researched for process multiply-and-accumulate operation which is used in deep neural networks efficiently. Conventional CIM architecture only supports binary neural network which has lower accuracy. Some approaches use capacitor for multi bit operation. However, because capacitor has large size, the area efficiency of CIM macro is degraded. This paper proposes CIM macro structure that supports multi bit operation using parasitic capacitance of transistor. The proposed structure does not need additional capacitor and thus, it can achieve area efficient multi bit operation.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129561762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Auto-tracking Method with Optimal Reference Voltage for PAM-4 Receiver PAM-4接收机最优参考电压自动跟踪方法
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613866
Daeho Yun, D. Jeong
{"title":"Auto-tracking Method with Optimal Reference Voltage for PAM-4 Receiver","authors":"Daeho Yun, D. Jeong","doi":"10.1109/ISOCC53507.2021.9613866","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613866","url":null,"abstract":"This paper presents an auto-tracking method with an optimal reference voltage for a PAM-4 receiver. The auto-tracking optimal reference voltage circuit includes a center detector and a counter circuit that automatically finds optimal reference voltage directions in additions, three samplers, and a phase interpolator (PI) used in the existing normal operation of PAM-4. The key feature of the proposed circuit is to find a direction of the reference voltage of three samplers in a PAM-4 receiver and apply the final determined reference voltage of the sampler in normal operation. The circuit is implemented in 40-nm CMOS technology, and the area added to the existing PAM-4 receiver for finding reference voltage operation is 30x100 um2. The simulated proposed circuit consumes an average power of 221uW with a 4-GHz auto-tracking sampling clock.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127151983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Local and Global Activities of Izhikevich Neuron Model in Networks 网络中Izhikevich神经元模型的局部和全局活动
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613867
Y. Uwate, Y. Nishio, M. Obien, U. Frey
{"title":"Local and Global Activities of Izhikevich Neuron Model in Networks","authors":"Y. Uwate, Y. Nishio, M. Obien, U. Frey","doi":"10.1109/ISOCC53507.2021.9613867","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613867","url":null,"abstract":"It is important to investigate the phenomena in networks composed of neuron models. In our previous work, we have proposed a method to explain the phenomena in the whole network by nonlinear time-series analysis. In this study, we will clarify the relationship between the phenomena at the constituent nodes of the network and the overall phenomena.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127545596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power Consumption Analysis of a Fractional Approach to BANs Time Synchronization 一种分式ban时间同步方法的功耗分析
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613945
G. Avitabile, K. Man, A. Florio
{"title":"Power Consumption Analysis of a Fractional Approach to BANs Time Synchronization","authors":"G. Avitabile, K. Man, A. Florio","doi":"10.1109/ISOCC53507.2021.9613945","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613945","url":null,"abstract":"The paper analyzes the performance in terms of power saving of a novel very simple time synchronization algorithm mainly thought for Body Area Networks (BANs). The core of the approach is a fractional-timer concept, borrowed from the Phase-Locked Loops (PLL) theory, and a heuristic routine managing the on/off switching of the radio section of the device.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129975939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hardware Efficient Built-in Self-test Architecture for Power and Ground TSVs in 3D IC 3D集成电路中电源和接地tsv的硬件高效内置自检架构
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613959
Donghyun Han, Youngkwang Lee, Sooryeong Lee, Sungho Kang
{"title":"Hardware Efficient Built-in Self-test Architecture for Power and Ground TSVs in 3D IC","authors":"Donghyun Han, Youngkwang Lee, Sooryeong Lee, Sungho Kang","doi":"10.1109/ISOCC53507.2021.9613959","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613959","url":null,"abstract":"3D integrated circuits (3D ICs) based on through- silicon vias (TSVs) are widely used as a solution to solve the interconnect and power problems in IC design. However, as the structures of 3D ICs become more complex, testing has emerged as an important challenge. It is difficult to test power and ground TSVs because they are connected to a grid after stacking. In this paper, a built-in self-test architecture for power and ground TSVs is proposed. This architecture tests for three types of TSV faults that are critical to the operation of TSVs. The proposed test architecture can improve the reliability of 3D stacked IC by providing a suitable test for power and ground TSVs with little hardware overhead.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"95 16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129145028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Self-coupled MASH Delta-Sigma Modulator with Zero Optimization 零优化自耦合MASH δ - σ调制器
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613903
Jingying Zhang, Yang Zhao, Mingyi Chen, Chixiao Chen, Fan Ye, Liang Qi
{"title":"Self-coupled MASH Delta-Sigma Modulator with Zero Optimization","authors":"Jingying Zhang, Yang Zhao, Mingyi Chen, Chixiao Chen, Fan Ye, Liang Qi","doi":"10.1109/ISOCC53507.2021.9613903","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613903","url":null,"abstract":"This paper presents a discrete time (DT) self-coupled multi-stage noise-shaping (MASH) delta-sigma modulator (DSM) with zero optimization. Zero optimization scheme is incorporated into the self-coupled path between the MASH stages, thus generating a desired notch in the band edge for the leaked quantization noise. When compared with a general self-coupled path, the employment of zero optimization can further mitigate the quantization noise leakage. Moreover, this zero-optimization scheme can be easily implemented by changing the coefficient of the self-coupled path. Therefore, it does not impose any additional hardware consumption. A 2+2 MASH DSM was built in the Matlab Simulink to demonstrate its principle. Simulation results show that the proposed architecture relaxed the DC gain requirements for the integrators further.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132498848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Gain Boosted Single-Ended 300 GHz InP HBT Oscillator for Terahertz Applications 用于太赫兹应用的增益增强单端300 GHz InP HBT振荡器
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613895
Waseem Abbas, M. Seo
{"title":"A Gain Boosted Single-Ended 300 GHz InP HBT Oscillator for Terahertz Applications","authors":"Waseem Abbas, M. Seo","doi":"10.1109/ISOCC53507.2021.9613895","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613895","url":null,"abstract":"This work presents a novel single-ended, gain boosted 250 nm indium phosphide (InP) heterojunction bipolar transistor (HBT) based oscillator in the terahertz frequency range. An embedding network is added with common emitter HBT to boost the feedback gain from Gma (Maximum Available Gain) to Gmax (Maximum Achievable Gain). The achieved output power is 5 dBm at 304.5 GHz and it consumes only 114 mW. The phase noise is -82 dBc/Hz at 1 MHz offset frequency. The proposed oscillator can be used for submillimeter-wave and next-generation integrated circuit applications like THz imaging and sensing.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125566239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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