Background Timing-Skew Mismatch Calibration for Time-Interleaved ADCs

Abstract

Time-interleaved ADC is widely used in high-speed applications. This structure can increase the effective sampling rate of the entire converter by multiplexing multiple ADCs in parallel. However, this architecture will be affected by mismatches between different sub-converters, including offset, gain, and timing. Timing skew will produce dynamic errors, thus posing a greater challenge. This paper presents recent state-of-the-art solutions addressing the timing skew mismatch in TI ADC through two types of background blind calibration techniques: a) methods based on deterministic equalization and b) techniques based on statistical information of the input signal.