Early HW/SW Co-Verification Using Virtual Platforms

Abstract

Early HW/SW co-verification is important to minimize the product time-to-market. In this paper, a new VP (virtual platform) technique is introduced where two heterogeneous simulators, i.e., SystemC and RTL, communicate with each other through IPC (Inter Process Communication). Experimental results show how the proposed approach contributes to shorten VP debugging TAT (turn-around time) and shift-left HW/SW co-verification before FPGA is available. In addition, the proposed method shows a reduction in a setup time for a new platform where VP and HW emulator are combined to accelerate the simulation speed.