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2021 18th International SoC Design Conference (ISOCC)最新文献

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High-Level Synthesis of Approximate Computing Circuits with Dual Accuracy Modes 双精度模式近似计算电路的高级综合
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9614001
Kenta Shirane, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama
{"title":"High-Level Synthesis of Approximate Computing Circuits with Dual Accuracy Modes","authors":"Kenta Shirane, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama","doi":"10.1109/ISOCC53507.2021.9614001","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9614001","url":null,"abstract":"This paper presents high-level synthesis techniques for approximate computing circuits with dual accuracy modes. At the exact mode, the generated circuits compute accurately but slowly. At the approximate mode, on the other hand, the circuits compute inaccurately but quickly. Thus, the proposed techniques enable the circuits to optimize the tradeoff between accuracy and performance at runtime.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133857145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Pre-RTL DNN Hardware Evaluator With Fused Layer Support Pre-RTL DNN硬件评估器与融合层的支持
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9614027
Chih-Chyau Yang, Tian-Sheuan Chang
{"title":"Pre-RTL DNN Hardware Evaluator With Fused Layer Support","authors":"Chih-Chyau Yang, Tian-Sheuan Chang","doi":"10.1109/ISOCC53507.2021.9614027","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9614027","url":null,"abstract":"With the popularity of the deep neural network (DNN), hardware accelerators are demanded for real time execution. However, lengthy design process and fast evolving DNN models make hardware evaluation hard to meet the time to market need. This paper proposes a pre-RTL DNN hardware evaluator that supports conventional layer-by-layer processing as well as the fused layer processing for low external bandwidth requirement. The evaluator supports two state-of-the-art accelerator architectures and finds the best hardware and layer fusion group. The experimental results show the layer fusion scheme can achieve 55.6% memory bandwidth reduction, 36.7% latency improvement and 49.2% energy reduction compared with layer-by-layer operation.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133806568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Stochastic Variable Gain Amplifier Adaptation for PAM-4 signaling PAM-4信号的随机变增益放大器适配
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613986
Minkyo Shim, Woonghee Lee, Yunhee Lee, D. Jeong
{"title":"A Stochastic Variable Gain Amplifier Adaptation for PAM-4 signaling","authors":"Minkyo Shim, Woonghee Lee, Yunhee Lee, D. Jeong","doi":"10.1109/ISOCC53507.2021.9613986","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613986","url":null,"abstract":"This paper presents a stochastic variable gain amplifier (VGA) adaptation method for a four-level pulse amplitude modulation (PAM-4) signaling. Two error samplers and three data samplers are used per clock, and two sets of such samples from two sequential unit intervals (UIs) are detected. The weighted summation of 36 symbol histograms is used for VGA adaptation. The weight of each symbol is calculated using Bayes’ theorem. The stochastic VGA adaptation enables settlements to the lock point even with a closed eye while a sign-sign least mean square (SSLMS) algorithm fails to lock. Even though the number of error samplers is reduced for high clocking power efficiency, the proposed stochastic adaptation utilizes eight more transitions than the SSLMS, resulting in a shorter adaptation time compared with the SSLMS algorithm.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"300 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116597265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Machine Learning based Prior-Knowledge-Free Nyquist ADC Characterization and Calibration 基于机器学习的无先验知识奈奎斯特ADC表征与校准
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613864
Danfeng Zhai, Chixiao Chen, Liang Qi, Fan Ye, Junyan Ren
{"title":"Machine Learning based Prior-Knowledge-Free Nyquist ADC Characterization and Calibration","authors":"Danfeng Zhai, Chixiao Chen, Liang Qi, Fan Ye, Junyan Ren","doi":"10.1109/ISOCC53507.2021.9613864","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613864","url":null,"abstract":"Traditional ADC characterization and calibration algorithms, for example, least mean square, was based on sophisticated ADC modeling knowledge. The recent artificial intelligence surge motivates us to develop a general and prior-knowledge-free method suitable to a variety of ADC distortion sources. This paper describes such a method using neural network. The input of the network is bit-wisely encoded, and the network utilizes a residual topology for fast convergence. A number of Nyquist ADC prototypes, including an open-loop amplifier based pipelined SAR ADCs, an NMOS based sampling circuit etc., are characterized or calibrated by adopting the machine learning based methods. Measurement results shows the improvement is nearly 30dB SFDR.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116654483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design Techniques for Area-efficient Two-Stacked Current Sources in Nanometer CMOS Technology 纳米CMOS技术中面积高效的双堆叠电流源设计技术
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613881
Dongjun Lee, Jaeduk Han
{"title":"Design Techniques for Area-efficient Two-Stacked Current Sources in Nanometer CMOS Technology","authors":"Dongjun Lee, Jaeduk Han","doi":"10.1109/ISOCC53507.2021.9613881","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613881","url":null,"abstract":"Employing long-channel transistors for building current sources increases the analog circuit area because of complicated design rules associated with the use of long channel transistors, especially in advanced CMOS technologies. Therefore, stacked short-channel transistors are preferred for current source construction; however, they require proper design techniques. In this paper, we propose two-stacked current source design techniques, along with small- and large-signal graphical analyses. The results reveal that two-stacked current sources can achieve high output resistance and high current density with a properly determined width ratio.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116663112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
ASIC Implementation of Magnetic Induction based Wireless Communication System 磁感应无线通信系统的ASIC实现
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9614024
Jaehyuk So, Dong-Hyun Lee, Min-Joon Kim, Yeonsoo Moon
{"title":"ASIC Implementation of Magnetic Induction based Wireless Communication System","authors":"Jaehyuk So, Dong-Hyun Lee, Min-Joon Kim, Yeonsoo Moon","doi":"10.1109/ISOCC53507.2021.9614024","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9614024","url":null,"abstract":"In this paper, the ASIC design result of magnetic induction for wireless communication system is presented. Magnetic induction system is designed for measurement of distance and sensing status of river bed. The system has a low-power design because it has to be buried in the river bed for a long time. We implemented FPGA board to verify this system, and designed ASIC including digital modem block. Power consumption is 75mW, but real power we expect is low because the system has wake-up function for special case. Digital block gate count is 82k in TSMC 0.13um bcd plus process.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116814540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of Layout Arrangment for CMOS Oscillators to Reduce Overall Variation on Wafer 减少晶圆上整体变化的CMOS振荡器布局分析
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613955
Pang-Yen Lou, Y. Ho, Chua-Chin Wang
{"title":"Analysis of Layout Arrangment for CMOS Oscillators to Reduce Overall Variation on Wafer","authors":"Pang-Yen Lou, Y. Ho, Chua-Chin Wang","doi":"10.1109/ISOCC53507.2021.9613955","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613955","url":null,"abstract":"This investigation demonstrates the analysis of various layout arrangements for oscillators (OSC) realized by CMOS technologies. More importantly, the analysis shows that the serpentine style of OSC stages (tiles) attains the minimum variation on wafer. Based on the analytic solution, various OSCs realized using 0.18 μm CMOS process, where the chip area of 1.458×0.908 mm2, are simulated to justify the robustness of the proposed layout arrangement.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122041833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power-efficient VCO-based ADCs for Wireless Communication Systems 无线通信系统中基于vco的高能效adc
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613925
Xinpeng Xing, Xueqian Shang, S. Liu, Xinfa Zheng, G. Gielen
{"title":"Power-efficient VCO-based ADCs for Wireless Communication Systems","authors":"Xinpeng Xing, Xueqian Shang, S. Liu, Xinfa Zheng, G. Gielen","doi":"10.1109/ISOCC53507.2021.9613925","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613925","url":null,"abstract":"CMOS technology scaling imposes decreased amplifier intrinsic gain and limited headroom voltage on analog-to-digital converter (ADC) design. On the other hand, digital gates improve their speed and power efficiency continuously in advanced processes. One competitive solution to these design challenges is using highly digital time-domain ADC architecture, featured by analog-to-time converters, including voltage-controlled oscillators (VCOs) and pulse width modulators (PWMs). This paper summarizes the design of power-efficient VCO-based oversampling ADCs, one 0-1 multi-stage shaping (MASH) VCO-based ADC and the other 0-2 MASH structure, focusing on both architecture- and block-level innovations. Experimental results in 40nm CMOS demonstrate their capabilities of state-of-the-art power efficiencies and high signal bandwidth, indicating their potential applications in wireless communications such as 5/6G and WiFi 6.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124649986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Haar Classifier Accelerator with Reduced Multiplexer Usage 减少多路复用器使用的Haar分类器加速器
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613971
Sanghyun Lee, Byungin Moon
{"title":"A Haar Classifier Accelerator with Reduced Multiplexer Usage","authors":"Sanghyun Lee, Byungin Moon","doi":"10.1109/ISOCC53507.2021.9613971","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613971","url":null,"abstract":"A Haar classifier accelerator is widely used in embedded vision systems because it can detect faces rapidly and accurately. However, implementing the Haar classifier accelerator requires considerable hardware resources, many of which are multiplexers used to extract integral values within a sub-window. Therefore, to decrease the multiplexer usage in the Haar classifier accelerator, we propose a method that reduces the sub-window size by excluding some rows and columns of the sub-window from integral value extraction. The proposed method considerably reduces the multiplexer usage than that of the conventional method while maintaining the detection rate and the number of false detections.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129188380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
ChaCha20-Poly1305 Crypto Core Compatible with Transport Layer Security 1.3 ChaCha20-Poly1305加密核心兼容传输层安全1.3
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9614016
Ronaldo Serrano, Ckristian Duran, Trong-Thuc Hoang, Marco Sarmiento, Akira Tsukamoto, K. Suzaki, C. Pham
{"title":"ChaCha20-Poly1305 Crypto Core Compatible with Transport Layer Security 1.3","authors":"Ronaldo Serrano, Ckristian Duran, Trong-Thuc Hoang, Marco Sarmiento, Akira Tsukamoto, K. Suzaki, C. Pham","doi":"10.1109/ISOCC53507.2021.9614016","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9614016","url":null,"abstract":"The security of the information represents a vital part of all communications protocols. In computer networks, Transport Layer Security (TLS) represents the majority of the use of secure channels for end-to-end communications. However, the efforts are directed only to optimize the software implementations. This paper shows an Authenticated Encryption with Associated Data (AEAD) hardware implementation of ChaCha20-Poly1305 compatible with TLS 1.3. Compared to a software implementation in a RISC-V environment, the performance increase by 7. The AEAD implementation reaches a speed of 21.5-cycle/byte.×The design is implemented in Xilinx Virtex-7 XC7VX485T Field-Programmable Gate Array (FPGA), using 7897 Look-Up Tables (LUT) and 4840 Flip-Flops (FF), represented in 26% of ChaCha20 and 54% of Poly1305.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"383 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127821079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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