Power-efficient VCO-based ADCs for Wireless Communication Systems

CMOS technology scaling imposes decreased amplifier intrinsic gain and limited headroom voltage on analog-to-digital converter (ADC) design. On the other hand, digital gates improve their speed and power efficiency continuously in advanced processes. One competitive solution to these design challenges is using highly digital time-domain ADC architecture, featured by analog-to-time converters, including voltage-controlled oscillators (VCOs) and pulse width modulators (PWMs). This paper summarizes the design of power-efficient VCO-based oversampling ADCs, one 0-1 multi-stage shaping (MASH) VCO-based ADC and the other 0-2 MASH structure, focusing on both architecture- and block-level innovations. Experimental results in 40nm CMOS demonstrate their capabilities of state-of-the-art power efficiencies and high signal bandwidth, indicating their potential applications in wireless communications such as 5/6G and WiFi 6.