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2021 18th International SoC Design Conference (ISOCC)最新文献

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CTT-based Non-Volatile Deep Neural Network Accelerator Design 基于ctt的非易失性深度神经网络加速器设计
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613930
Yang Xiao, Wuyu Fan, Yuan Du, Li Du, Mau-Chung Frank Chang
{"title":"CTT-based Non-Volatile Deep Neural Network Accelerator Design","authors":"Yang Xiao, Wuyu Fan, Yuan Du, Li Du, Mau-Chung Frank Chang","doi":"10.1109/ISOCC53507.2021.9613930","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613930","url":null,"abstract":"CMOS-compatible Charge-Trap Transistor (CTT) has empowered Non-Volatile Memory (NVM) and Compute-in-Memory (CiM) applications using its threshold voltage (VTH) programmability. In the paper, we characterized the threshold voltage tuning behavior of CTTs and built the simulation model based on silicon data in 28nm CMOS technology. With the established model, we discussed the design methodology and performance evaluation of non-volatile Deep Neural Network (DNN) accelerators. This paper also summarizes the previous work that CTT is used as an analog multiplier for a DNN accelerator. Then, as a new proof-of-concept design, a CTT-based CiM structure was proposed with normal NVM and computing two operation modes.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130369563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Linear Array Mutual Coupling Compensation Technique for Angle of Arrival Estimation 一种用于到达角估计的线阵互耦补偿技术
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9614022
A. Florio, G. Avitabile
{"title":"A Linear Array Mutual Coupling Compensation Technique for Angle of Arrival Estimation","authors":"A. Florio, G. Avitabile","doi":"10.1109/ISOCC53507.2021.9614022","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9614022","url":null,"abstract":"The paper introduces a linear compensation technique suitable for Uniform Linear Arrays (ULAs) of microstrip antennas employed for phase critical applications like Angle-of-Arrival estimation. The mathematical discussion is offered and first simulations are presented in order to validate the proposed approach.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130497005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Local Bit-line Charge-sharing based Pre-charging SRAM for Near Threshold Voltage Operation 基于本地位线电荷共享的近阈值电压预充电SRAM
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613896
Hyunchul Park, Jongsun Park
{"title":"Local Bit-line Charge-sharing based Pre-charging SRAM for Near Threshold Voltage Operation","authors":"Hyunchul Park, Jongsun Park","doi":"10.1109/ISOCC53507.2021.9613896","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613896","url":null,"abstract":"Recent SRAM in System-on-Chip (SoC) is required to consume as low power as possible while maintaining its performance and reliability. Lowering supply voltage is an efficient way to reduce power consumption in SRAM. However, SRAM operation becomes highly unstable when its supply voltage is in Near-Threshold Voltage (NTV) region. In this paper, we propose a local bit-line charge-sharing based pre-charging SRAM cell which can sustain performance under NTV region. The proposed cell shows improved read stability in NTV region compared to the previous cells. In addition, by employing transmission gate as access transistors in the proposed cell, better read performance has been achieved at ISO- VMIN condition. The simulation results using 28nm CMOS technology shows that the proposed SRAM cell achieves 2X large read SNM with x1.44 - x7.48 speed improvement.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128346730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CNN encryption using XOR Gate for Hardware Optimization 基于异或门的CNN加密硬件优化
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9614013
K. Lee, Sumin Lee, Sunghwan Joo, Hong Keun Ahn, Young Seok Jung, Seong-Ook Jung
{"title":"CNN encryption using XOR Gate for Hardware Optimization","authors":"K. Lee, Sumin Lee, Sunghwan Joo, Hong Keun Ahn, Young Seok Jung, Seong-Ook Jung","doi":"10.1109/ISOCC53507.2021.9614013","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9614013","url":null,"abstract":"Artificial intelligence networks have been researched in many fields such as computer vision, health care, and military service. Convolutional neural network (CNN) is one of the basic neural networks that uses convolutional operations as the basis to train data and perform desired application. However, important parameters used in CNN applications suffer from security issues. Thus, the need for data protection is increasing. The traditional approach of storing training data and weight parameters encrypted in external memory has the disadvantage of large hardware area. In this paper, the CNN-based encrypting method using XOR gates is proposed to reduce hardware resources by allowing encryption and decryption to operate in a single module. The proposed encrypting method reduces hardware usage by more than 100 times compared to the conventional encrypting method.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"501 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133848103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Detecting LED Chip Surface Defects with Modified Faster R-CNN 改进的更快R-CNN检测LED芯片表面缺陷
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613949
Zhiwen Zhang, Qian Gong, Yuan Cao, Cheng Yin, Enyi Yao, Yanhua Liu, Yongqing Pan
{"title":"Detecting LED Chip Surface Defects with Modified Faster R-CNN","authors":"Zhiwen Zhang, Qian Gong, Yuan Cao, Cheng Yin, Enyi Yao, Yanhua Liu, Yongqing Pan","doi":"10.1109/ISOCC53507.2021.9613949","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613949","url":null,"abstract":"LED surface defect detection is a vital procedure of quality control in the mass production of LEDs. Traditional methods rely on artificial vision, which requires experienced workers and is extremely low on efficiency. In this paper, we develop a new LED chip surface defect detection by the modified Faster R-CNN. The model is pre-trained on the dataset of COCO and then is fine-tuned on our collected LED surface dataset. The dataset consists of 1556 images which are labeled with 5 types of surface defects. Based on the experimental results on the collected dataset from the production line, the model can achieve over 79% mAP on our dataset.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131019138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Hardware-friendly Log-scale Quantization for CNNs with Activation Functions Containing Negative Values 具有负值激活函数的cnn的硬件友好对数尺度量化
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613921
Dahun Choi, Hyun Kim
{"title":"Hardware-friendly Log-scale Quantization for CNNs with Activation Functions Containing Negative Values","authors":"Dahun Choi, Hyun Kim","doi":"10.1109/ISOCC53507.2021.9613921","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613921","url":null,"abstract":"Recently, with the development of deep learning and GPU, various convolutional neural network (CNN)-based object detection studies are accelerating, and accordingly, research on network compression including quantization is being actively conducted. Due to the characteristics of CNN that accompanies multiple multiplication operations, it is difficult for the existing linear scale quantization method to maximize the benefits of network compression in the accelerator implementation process. On the other hand, log scale quantization has a good quantization effect when implementing an accelerator, but causes a relatively large decrease in accuracy. To address this problem, this paper proposes a technique that minimizes the accuracy degradation of CNNs due to quantization by re-scaling the distribution in consideration of the activation function with negative values in the log scale quantization process. As a result of the experiment, the proposed quantization technique can achieve an accuracy improvement of 1.6% compared to the existing log scale quantization, which can reduce hardware resources by more than 87.52% while maintaining a similar accuracy degradation compared to the existing linear scale quantization.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133060885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Data Protection Method for Flash Memory in Serial Peripheral Interface 串行外设接口中闪存的数据保护方法
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613871
Aeri Kim, Seokhyeong Kang
{"title":"Data Protection Method for Flash Memory in Serial Peripheral Interface","authors":"Aeri Kim, Seokhyeong Kang","doi":"10.1109/ISOCC53507.2021.9613871","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613871","url":null,"abstract":"We propose a general flash protection function for flash read/write/erase operations, to provide security for the contents. The ‘read protection’ changes all outputs of flash memory to specific data and the ‘write/erase protection’ ensures that all commands to flash memory are ignored. We also provide a function that can disable or restore the flash protection whenever a user wants by providing a valid password. The flash protection can be used in any kind of flash memory because it works at the Serial Peripheral Interface (SPI) level.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114609262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
LightNet: A Lightweight Neural Network for Image Classification LightNet:用于图像分类的轻量级神经网络
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613865
A. Sharma, Byungho Kang, Kyung Ki Kim
{"title":"LightNet: A Lightweight Neural Network for Image Classification","authors":"A. Sharma, Byungho Kang, Kyung Ki Kim","doi":"10.1109/ISOCC53507.2021.9613865","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613865","url":null,"abstract":"Image Classification is widely used in the field of computer vision that focuses on classifying the object in a given image. Lately, image classification techniques are not only restricted to computer applications but are also famous for edge devices. Convolutional Neural Networks play a crucial role in building a good image classifier. However, in order to achieve high accuracy, CNN algorithms lead to use a large number of layers that results in increasing the number of parameters and makes it difficult to implement on edge devices. To overcome this problem, a lightweight image classifier \"LightNet\" is proposed in this paper that makes use of different scales of receptive fields to extract more feature maps with fewer parameters. To examine the efficacy of the proposed lightweight classifier, it is tested on the CIFAR-10 dataset and got 90% accuracy by using only .26M parameters, which shows that the proposed Lightnet is very effective to be implemented on edge devices.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132181140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Implement Tunable Sub-TΩ On-chip Resistor for Vital Signal Acquisition: A Review 实现可调谐Sub-TΩ片上电阻的生命信号采集:综述
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613917
Mingyi Chen, Yuzhi Hao, Liang Qi, Yongfu Li, Jun Yan
{"title":"Implement Tunable Sub-TΩ On-chip Resistor for Vital Signal Acquisition: A Review","authors":"Mingyi Chen, Yuzhi Hao, Liang Qi, Yongfu Li, Jun Yan","doi":"10.1109/ISOCC53507.2021.9613917","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613917","url":null,"abstract":"Bio-amplifier is one of the most crucial building blocks of the wearable or implantable vital signal acquisition system. To achieve sub-hertz high-pass corner frequency (fHP), an on-chip resistor with extremely large resistance value on the order of sub-TΩ is demanded. This paper reviews the state-of-the-art sub-TΩ on-chip resistor implementation methods. By combining the advantages of different methods, a pseudo-resistor (PR) calibration circuit has been proposed, which is capable of amplifying the impedance of the switch-capacitor (SC) circuit via a feedback loop. As a result, the sub-hertz fHP can be determined by an external clock frequency, which has high robustness and tunability. Implemented in a standard 55nm CMOS process, the post-layout simulation results of the proposed circuitry have demonstrated its potential capability to be applied to vital signals acquisition.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132183007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A SAR ADC with Segment Binary Weighted Attenuation Capacitor DAC layout technique 一种分段二值加权衰减电容DAC布局技术的SAR ADC
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9614025
Keun-Yong Chung, K. Baek, Bo-Kyong Choi
{"title":"A SAR ADC with Segment Binary Weighted Attenuation Capacitor DAC layout technique","authors":"Keun-Yong Chung, K. Baek, Bo-Kyong Choi","doi":"10.1109/ISOCC53507.2021.9614025","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9614025","url":null,"abstract":"This paper presents a SAR ADC with segment binary weighted attenuation capacitor (BWA) DAC layout technique using custom routing capacitor is proposed. And there are simulation and measurement results. SAR DAC with segment BWA DAC linearity is sensitive at parasitic capacitor. There are 5 types of parasitic can be formed and they can explain in mathematical expression about MSB Top voltage. To reduce these parasitic capacitors to get good linearity, custom routing capacitors are proposed. Two of custom routing capacitors are top to top routing capacitor and top to bottom routing capacitor. They protect the MSBTOP to LSBBOT, MSBTOP to LSBTOP parasitic capacitor and reduce the LSBTOP to VSS parasitic capacitor and routing the attenuation capacitor to each MSB and LSB top plate. The proposed SAR ADC is 6.56 dB higher performance than SAR ADC without routing capacitor.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128207621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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