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2021 18th International SoC Design Conference (ISOCC)最新文献

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LSTM-based Temperature Prediction and Hotspot Tracking for Thermal-aware 3D NoC System 基于lstm的热感知三维NoC系统温度预测与热点跟踪
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613862
Tong Cheng, Haoyu Du, Li Li, Yuxiang Fu
{"title":"LSTM-based Temperature Prediction and Hotspot Tracking for Thermal-aware 3D NoC System","authors":"Tong Cheng, Haoyu Du, Li Li, Yuxiang Fu","doi":"10.1109/ISOCC53507.2021.9613862","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613862","url":null,"abstract":"As the increasingly large energy consumption and diverse workload distribution in many-core systems, thermal problems, especially hotspots, have become a significant restriction for the performance of the Network-on-Chip system. Therefore, several proactive thermal management methods based on thermal prediction data were proposed. However, previous temperature prediction methods did not consider the impact of hotspots, and their prediction accuracy is not satisfying. In this paper, we propose a Long Short-Term Memory (LSTM)-based temperature prediction and hotspot tracking model in a thermalaware 3D NoC system. As the experiment indicates, the Mean-Square-Error (MSE) of the 6-step temperature prediction of the proposed model is 0.411°C and the response time for tracking hotspot transfer is less than 0.075 ms.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128504010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Binary/Ternary Vector Matrix Multiplier with 3T-2R CBRAM Cell 二进制/三元矢量矩阵乘法器与3T-2R CBRAM单元
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613884
Hwan-Jin Joo, K. Kwon
{"title":"Binary/Ternary Vector Matrix Multiplier with 3T-2R CBRAM Cell","authors":"Hwan-Jin Joo, K. Kwon","doi":"10.1109/ISOCC53507.2021.9613884","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613884","url":null,"abstract":"The implementation of in-memory computing neuromorphic system is an open problem. In this paper, we present the CBRAM-based 3T-2R cell that support not only binary but also ternary and Vector Matrix Multiplier (VMM) using them. While a conventional neuromorphic system uses a current summing method, the proposed model derives XNOR bit operation through competition between pull-up and pulldown cells. The circuits are simulated in SPICE using IDEC 180nm CMOS process models, and CBRAM memristor models.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116645209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Low-Complexity Architecture for Implementing Square to Tenth Root of Complex Numbers 一种实现复数的平方根到十分方根的低复杂度结构
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613873
Jin Xu, Lin Jiang, Hui Chen, Yuxiang Fu, Li Li
{"title":"A Low-Complexity Architecture for Implementing Square to Tenth Root of Complex Numbers","authors":"Jin Xu, Lin Jiang, Hui Chen, Yuxiang Fu, Li Li","doi":"10.1109/ISOCC53507.2021.9613873","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613873","url":null,"abstract":"Implementing complex number Nth root with low-complexity hardware is challenging, especially for high-order Nth roots. Since the most commonly used values of N in Nth root computation are integers from 2 to 10, we propose a hardware-friendly architecture for computing square to tenth root of complex numbers, based on coordinate rotation digital computer (CORDIC). Through expanding the range of convergence, the proposed method can support the input range from 10-8 to 104 and reach the relative error of 10-6. Then we propose a pipelined architecture to implement it, utilizing the similarity in the N result solution process to reduce the complexity. The synthesized results confirm that the circuit complexity only increases 0.157% compared to calculating one result of the square root.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114457244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Sequential Two-step Algorithm For DC Offset Cancellation of PAM-4 Receiver PAM-4接收机直流偏置抵消的顺序两步算法
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613870
Yunhee Lee, Woonghee Lee, Minkyo Shim, D. Jeong
{"title":"A Sequential Two-step Algorithm For DC Offset Cancellation of PAM-4 Receiver","authors":"Yunhee Lee, Woonghee Lee, Minkyo Shim, D. Jeong","doi":"10.1109/ISOCC53507.2021.9613870","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613870","url":null,"abstract":"This paper presents an offset cancellation scheme for samplers in an analog front-end (AFE) of a four-level pulse amplitude modulation (PAM-4) receiver. Based on the analysis of the input-referred offset of a sampler, a two-step offset cancellation algorithm combined with a control loop of the voltage-mode digital-to-analog converter is proposed to separately calculate the offsets of samplers and other circuits in the AFE. In this manner, the dc offset of the receiver is substantially removed regardless of the amplitude of the PAM-4 signal.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116087544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Application on Demodulation of FBG Sensing Signals using Phase Detection Algorithm of Intake and Exhaust 进排气相位检测算法在光纤光栅传感信号解调中的应用
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613960
Chenjie Kong, Tianming Chen, Jun Zhang, Guizhong Jiang, Yuan Shen, Pan He
{"title":"Application on Demodulation of FBG Sensing Signals using Phase Detection Algorithm of Intake and Exhaust","authors":"Chenjie Kong, Tianming Chen, Jun Zhang, Guizhong Jiang, Yuan Shen, Pan He","doi":"10.1109/ISOCC53507.2021.9613960","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613960","url":null,"abstract":"Fiber Fabry-Perot tunable filter (FFP-TF) based fiber Bragg grating (FBG) demodulation has been widely applied in many areas, in which F-P etalon is commonly used as wavelength reference. The traditional demodulation algorithm requires the whole spectrum data of each cycle to calculate the sensing signal wavelength, seriously affecting the real-time performance. The spectrum of the fiber-optic F-P etalon is a uniform comb spectrum with a typical marker, similar to the engine crankshaft signal. When an engine runs at high speed, the intake and exhaust phase needs to be demodulated as soon as possible. In this paper, a low delay FBG sensing demodulation algorithm is proposed, drawing on the experience of the intake and exhaust phase demodulation algorithm. When the scanning speed is 1k Hz, the delay can be reduced more than ten times (e.g., from 0.1ms to 0.01ms).","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126884378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Short Word-Line Pulse with Fast Bit-Line Boosting For High Throughput 6T SRAM-based Compute In-memory Design 基于6T sram的高吞吐量内存计算设计中的快速位线提升短字行脉冲
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613869
Minseo Kim, Jongsun Park
{"title":"Short Word-Line Pulse with Fast Bit-Line Boosting For High Throughput 6T SRAM-based Compute In-memory Design","authors":"Minseo Kim, Jongsun Park","doi":"10.1109/ISOCC53507.2021.9613869","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613869","url":null,"abstract":"In order to get over the read disturbance in SRAM-based Compute In-Memory (CIM), 6T SRAM bit-cell with underdrived Word-Line (WL) has been widely adopted. However, underdrived WL suffers from slower Bit-Line (BL) discharge, which eventually increases the CIM latency. In this paper, we propose a short WL pulse with fast BL boosting technique. Short WL pulse approach can efficiently reduce the read disturbance while BL is discharged through BL boosting circuit so that fast BL discharging time is guaranteed with little area overhead and higher reliability. 6T SRAM bit-cell array with BL boosting has been implemented in CMOS 28nm process, and the discharging time is decreased by 63.0% compared to the conventional WL underdrive technique.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"7 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121003097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-Latency Architecture for Implementing Floating-Point Multiplier and Divider Based on Symmetric-Mapping LUT 基于对称映射LUT实现浮点乘法器和除法器的低延迟架构
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613909
Heping Yang, Hui Chen, Yuxiang Fu, Li Li
{"title":"Low-Latency Architecture for Implementing Floating-Point Multiplier and Divider Based on Symmetric-Mapping LUT","authors":"Heping Yang, Hui Chen, Yuxiang Fu, Li Li","doi":"10.1109/ISOCC53507.2021.9613909","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613909","url":null,"abstract":"The current multiplication and division IP imple- mentation are mainly achieved through LUT-based and iterative methods. This paper proposes a new hardware architecture, for fast calculating the multiplication and division of floating-point data. By mapping the multiplication and division operations to and , based on the mathematical characteristics of the two functions, Symmetric-Mapping LUT method can quickly calculate the floating-point multiplication and division, which has better low-latency characteristics and smaller area than that of the traditional method. The proposed multiplication and division architecture was synthesized under TSMC 40nm CMOS technology. The area is 14941.832µ at the frequency of 1GHz. On top of that, the proposed architecture reduces the latency to 3 cycles.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127133758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Novel In-memory Computing Circuit using Muller C-element 基于Muller c元的新型内存计算电路
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613964
S. Song, Youngmin Kim
{"title":"Novel In-memory Computing Circuit using Muller C-element","authors":"S. Song, Youngmin Kim","doi":"10.1109/ISOCC53507.2021.9613964","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613964","url":null,"abstract":"Nowadays, von Neumann based computing system is facing a von Neumann bottleneck due to data transfer between separated memory and processor units. Moreover, it results in large energy consumption and reduces overall performance. To solve this von Neumann bottleneck or memory wall, in-memory computing (IMC) has been researched recently. In-memory computing reduces energy consumption and improves performance in von Neumann architecture. This paper proposes a new IMC logic circuit using Muller C-element based on 8+T differential static random-access memory (8+T SRAM). The circuit provides NAND/NOR/XOR operations simultaneously with 40%, 20%, and 50% faster performance than conventional IMC, respectively.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127268999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of emotion recognition system using neuromorphic computing technique 基于神经形态计算技术的情绪识别系统设计
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9614009
B. Ajay, Madhav Rao
{"title":"Design of emotion recognition system using neuromorphic computing technique","authors":"B. Ajay, Madhav Rao","doi":"10.1109/ISOCC53507.2021.9614009","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9614009","url":null,"abstract":"Human facial expression offers a visual understanding of the underlying human emotions and are comprehensively tapped to automate workflow in the areas of robotics, security, and other assisted and interactive technologies. The paper proposes implementation of human facial emotion recognition (FER) using neuromorphic computing (NC) designed binary synaptic neural network (BSN). An architecture consisting of Viola-Jones (VJ) algorithm with local binary pattern (LBP) as two stage pre-processing steps followed by NC driven synaptic network was designed and investigated for image-based emotion recognition system. The BSN was designed and simulated in system verilog models to showcase an acceptable accuracy of 69.5% for the six targeted emotion classes. NC design showcased comparable classifier accuracy for the emotion recognition system, as that of binary neural network, implemented in the past.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122601775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Secure Scan Design through Pseudo Fault Injection 基于伪故障注入的安全扫描设计
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9614012
Seokjun Jang, Hyungil Woo, Sunghoon Kim, Sungho Kang
{"title":"Secure Scan Design through Pseudo Fault Injection","authors":"Seokjun Jang, Hyungil Woo, Sunghoon Kim, Sungho Kang","doi":"10.1109/ISOCC53507.2021.9614012","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9614012","url":null,"abstract":"In order to improve testability of the chips, scan-based test is widely adopted as the DFT technique. However, the inserted scan chains can also be exploited as side-channel for an attack by a malicious user, it becomes a serious threat. In this paper, a low-cost secure scan design using a pseudo fault injection method is proposed. The proposed design disables normal output of the scan data through fault injection for unauthorized users with small area overhead, and the proposed method makes it difficult to check whether obfuscation is made even for the incorrect test key input.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122773700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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