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2021 18th International SoC Design Conference (ISOCC)最新文献

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Optimized Method for Thermal Tracking in 3D NoC Systems by Using ANN 基于神经网络的三维NoC系统热跟踪优化方法
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9614010
Menghao Guo, Tong Cheng, Li Li, Yuxiang Fu
{"title":"Optimized Method for Thermal Tracking in 3D NoC Systems by Using ANN","authors":"Menghao Guo, Tong Cheng, Li Li, Yuxiang Fu","doi":"10.1109/ISOCC53507.2021.9614010","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9614010","url":null,"abstract":"In this paper, we improve the thermal sensor allocation method based on the correlation between each node in the Network on Chip (NoC) system by tracking temperature under different scenarios. Moreover, an artificial neural network (ANN) is used to estimate the full-chip temperature distribution for the first time. Compared with the state of the art methods, our method can improve the average accuracy of the estimated results under different scenarios by 32.0% to 95.5%.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127723188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Mitigating IR-Drop with Design Technology Co-Optimization for Sub-Nanometer Node Technology 亚纳米节点技术设计技术协同优化降低ir下降
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9614021
D. Lee, Heecheol Hwang, Hyunteck Oh, Yongchan James Ban
{"title":"Mitigating IR-Drop with Design Technology Co-Optimization for Sub-Nanometer Node Technology","authors":"D. Lee, Heecheol Hwang, Hyunteck Oh, Yongchan James Ban","doi":"10.1109/ISOCC53507.2021.9614021","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9614021","url":null,"abstract":"In this paper, we have proposed various approaches for reducing IR (Voltage)-drop with the best trade-off between the PPA (performance, power, area) and the IR tolerance for sub-nanometer node designs and technologies. The proposed approaches include the optimization of power distribute network (PDN), clock-cell placement, and cell placement in logic paths.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"268 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121444011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Load-Independent Inverse Class-E Oscillator with Armstrong-Oscillator Based Topology 基于Armstrong-Oscillator拓扑的负载无关逆e类振荡器
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613877
Yutaro Komiyama, Shuya Matsuhashi, Wenqi Zhu, Kien Nguyen, H. Sekiya
{"title":"Load-Independent Inverse Class-E Oscillator with Armstrong-Oscillator Based Topology","authors":"Yutaro Komiyama, Shuya Matsuhashi, Wenqi Zhu, Kien Nguyen, H. Sekiya","doi":"10.1109/ISOCC53507.2021.9613877","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613877","url":null,"abstract":"This paper proposes the load-independent inverse class-E oscillator with Armstrong-oscillator based topology. The proposed oscillator achieves constant output voltage and soft switching against load variations due to the load-independent design. Moreover, the proposed circuit realizes the self-tuning function using the Armstrong-oscillator topology. As a result, the oscillator can also have robustness against the variations in the resonant frequency. The experimental results showed the effectiveness of the proposed oscillator.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122590456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Digital LDO with reference-less adaptive CLK generation and bit-shifting Coarse–Fine-control 具有无参考自适应CLK生成和位移粗-精细控制的数字LDO
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9614003
Woo-Hyoung Choi, Seung-Myeong Yu, Yunha Kang, Junyoung Song
{"title":"Digital LDO with reference-less adaptive CLK generation and bit-shifting Coarse–Fine-control","authors":"Woo-Hyoung Choi, Seung-Myeong Yu, Yunha Kang, Junyoung Song","doi":"10.1109/ISOCC53507.2021.9614003","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9614003","url":null,"abstract":"Conventional digital low dropout regulator (DLDO) operating speed is invariable due to constant external reference clock. Fixed DLDO operating speed, regardless of the load state, cause inefficient power consumption for steady-state load or stability problem due to slow transient response time. This paper introduces DLDO with reference-less adaptive clock generation which is optimized by load states. Coarse-fine control and burst-mode are added to the shift register adjusting power transistors (PT) to achieve a fast transient response. The proposed DLDO is designed in 180nm BCDMOS and operates at 1.8V with an output voltage of 1.5V. The maximum and minimum operating frequency is 393MHz, 165MHz respectively. Settling time is 174ns at load current changes from 2mA to 10mA.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126288271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Circular-based TSV Repair Architecture 基于循环的TSV修复体系结构
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613904
Youngkwang Lee, Donghyun Han, Sooryeong Lee, Sungho Kang
{"title":"A Circular-based TSV Repair Architecture","authors":"Youngkwang Lee, Donghyun Han, Sooryeong Lee, Sungho Kang","doi":"10.1109/ISOCC53507.2021.9613904","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613904","url":null,"abstract":"The previous TSV repair architectures can efficiently repair the TSV with only a few redundant-TSVs (RTSVs), but it requires a long repair path analysis time and a large repair path analyzer to get a high repair rate. This paper proposes a novel TSV repair architecture that can quickly analyze the repair path while ensuring a high repair rate. Experimental results show that the worst repair path analysis time of the proposed architecture with N signal-TSVs (STSVs) does not exceed 2N clock cycle. It also shows that the repair rate of the proposed architecture is not low compared to the previous architectures.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"111 49","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113944689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
ISOCC 2021 Cover Page ISOCC 2021封面
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613890
{"title":"ISOCC 2021 Cover Page","authors":"","doi":"10.1109/ISOCC53507.2021.9613890","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613890","url":null,"abstract":"","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"60 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113987570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficient Partial Sum Architecture and Memory Reduction Method for SC-Flip Polar Decoder sc -翻转极化译码器的高效部分和结构及内存缩减方法
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613860
J. Roh, Useok Lee, Yongje Lee, M. Sunwoo
{"title":"Efficient Partial Sum Architecture and Memory Reduction Method for SC-Flip Polar Decoder","authors":"J. Roh, Useok Lee, Yongje Lee, M. Sunwoo","doi":"10.1109/ISOCC53507.2021.9613860","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613860","url":null,"abstract":"To improve the error correction performance of successive cancellation (SC) decoding of polar codes, SC-flip (SCF) decoding was proposed. However, it requires large additional memory to save the decoding history for hardware implementation. This paper proposes a partial sum (PS) memory reduction method and a PS architecture for SCF decoders. We analyze the fractal structure of the generator matrix and propose a logic circuit to decide the corresponding row of the generator matrix for an arbitrary bit-index. The proposed design was implemented on the Xilinx Virtex-7 FPGA, which can reduce the number of flip-flops by up to 47% and the PS history memory size by 94% compared to other PS architectures.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123859106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 7.68 GHz Fast-Lock Low-Jitter Digital MDLL 一种7.68 GHz快速锁定低抖动数字多路并行电路
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613940
Junghoon Jin, Seungjun Kim, Sunguk Choi, Pil-Ho Lee, S. Rhee, Ki-hwan Choi, Jongsun Kim
{"title":"A 7.68 GHz Fast-Lock Low-Jitter Digital MDLL","authors":"Junghoon Jin, Seungjun Kim, Sunguk Choi, Pil-Ho Lee, S. Rhee, Ki-hwan Choi, Jongsun Kim","doi":"10.1109/ISOCC53507.2021.9613940","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613940","url":null,"abstract":"A 7.68 GHz fast-lock digital multiplying delay-locked loop (MDLL) is presented. Implemented in a 40-nm 1.2-V CMOS process, the proposed MDLL achieves an output frequency of 7.68 GH with a high frequency multiplication factor N = 64. By adopting a cyclic Vernier TDC, the proposed MDLL achieves a fast lock time of 6 reference cycles. To reduce jitter integration caused by power supply noise, a differential pair based digitally controlled oscillator (DCO) is adopted. Also, to reduce deterministic jitter, a DSM-based dithering jitter reduction scheme has been adopted. The proposed MDLL achieves a simulated p-p jitter of about 16 ps at 7.68 GHz. It occupies an active area of 0.026 mm2, and dissipates 29 mW at 7.68 GHz.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124206344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Novel Performance Evaluation Approach of AMBA AXI-Based SoC Design 基于AMBA轴的SoC设计性能评估新方法
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613920
T. Tan, Phap Duong-Ngoc, Thang Xuan Pham, Hanho Lee
{"title":"Novel Performance Evaluation Approach of AMBA AXI-Based SoC Design","authors":"T. Tan, Phap Duong-Ngoc, Thang Xuan Pham, Hanho Lee","doi":"10.1109/ISOCC53507.2021.9613920","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613920","url":null,"abstract":"The Advanced Microcontroller Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) presented by Arm is a bus oriented interface for on-chip communication. In addition to verifying bus functionalities, performance evaluation is an important process should be carefully considered to ensure the operation of a design. This paper introduces a novel method to measure the performance of an AMBA-based SoC design. By employing an SoC design using SystemVerilog and Universal Verification Methodology (UVM) on a license-free EDA Playground platform, transactions are transmitted successfully between managers and subordinates in the system. Moreover, the bandwidth and latency of the design are successfully measured using the proposed approach.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127882558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Multi-Bit In-Memory-Computing SRAM Macro Using Column-Wise Charge Redistribution for DNN Inference in Edge Computing Devices 在边缘计算设备中使用列向电荷再分配用于DNN推理的多比特内存计算SRAM宏
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613934
Changseon Chae, Subin Kim, Jong-Moon Choi, Jun-Eun Park
{"title":"A Multi-Bit In-Memory-Computing SRAM Macro Using Column-Wise Charge Redistribution for DNN Inference in Edge Computing Devices","authors":"Changseon Chae, Subin Kim, Jong-Moon Choi, Jun-Eun Park","doi":"10.1109/ISOCC53507.2021.9613934","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613934","url":null,"abstract":"This paper presents a charge-redistribution inmemory-computing (IMC) macro that realizes multi-bit multiply-and-accumulation (MAC) operation based on 5T static random-access memory (SRAM). The charge-domain MAC operation based on capacitor array allows the IMC-SRAM macro to achieve high linearity and improved energy efficiency. Also, an optimized 5T SRAM structure saves area consumption, increasing bit density of the macro. The proposed IMC-SRAM 64 × 64 macro was designed using 28nm CMOS process.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121200204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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