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LSMQ: A Layer-Wise Sensitivity-Based Mixed-Precision Quantization Method for Bit-Flexible CNN Accelerator LSMQ:基于分层灵敏度的位柔性CNN加速器混合精度量化方法
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613969
Yimin Huang, Kai Chen, Zhuang Shao, Yichuan Bai, Yafeng Huang, Yuan Du, L. Du, Zhongfeng Wang
{"title":"LSMQ: A Layer-Wise Sensitivity-Based Mixed-Precision Quantization Method for Bit-Flexible CNN Accelerator","authors":"Yimin Huang, Kai Chen, Zhuang Shao, Yichuan Bai, Yafeng Huang, Yuan Du, L. Du, Zhongfeng Wang","doi":"10.1109/ISOCC53507.2021.9613969","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613969","url":null,"abstract":"Model quantization is a prevailing way to accelerate convolutional neural network (CNN). Quantization with mixed precision tends to compress the model better and further improves the computation efficiency. However, it is challenging to identify the optimal bit width for each layer. In this paper, we proposed a mixed-precision quantization(LSMQ) method based on layer-wise sensitivity. We calculated the sensitivity of each layer first, then the weight of each layer would be automatically quantized with unique precision determined by the sensitivity ranking and a valid search strategy without retraining. Moreover, we presented a bit-flexible CNN accelerator that can efficiently support data operations with varying bit widths after mixed-precision quantization. Experiment on LSMQ shows that the top-1 accuracy for VGG16 based on the LSMQ method is 7.31% higher, while the model size is 3.4% smaller compared with previous work.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132773439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Triple-Rail Stochastic Number and Its Applications 三轨随机数及其应用
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613953
Sho Kawaminami, S. Yamashita
{"title":"Triple-Rail Stochastic Number and Its Applications","authors":"Sho Kawaminami, S. Yamashita","doi":"10.1109/ISOCC53507.2021.9613953","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613953","url":null,"abstract":"In Stochastic Computing (SC), we use bit-strings called stochastic numbers (SNs) to perform calculations in very low-cost hardware modules. In SC the length of SNs should be very long, so we need enough precision; the necessary cycles to perform calculations with SNs should be long. To mitigate this disadvantage, there proposed a method to use two shorter bit-strings to represent a single SN; the two bit-strings are called a dual-rail SN, and it is reported that it can reduce the necessary cycles with some additional hardware overhead and some calculation errors. In this paper, we further seek this direction, i.e., we propose to use three bit-strings called triple-rail SNs which needs much shorter cycles than dual-rail and conventional SNs. We compare triple-rail, dual-rail and conventional SNs in terms of hardware overhead and calculation errors.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115007080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Single-Inductor Triple-Source Energy Harvesting Interface for Batterty-Assisted IoT Applications 用于电池辅助物联网应用的单电感三源能量收集接口
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613848
Ming-Jie Chung, Chih-Lun Lo, Po-Hung Chen
{"title":"A Single-Inductor Triple-Source Energy Harvesting Interface for Batterty-Assisted IoT Applications","authors":"Ming-Jie Chung, Chih-Lun Lo, Po-Hung Chen","doi":"10.1109/ISOCC53507.2021.9613848","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613848","url":null,"abstract":"This paper presents a high-efficiency single-inductor triple-source energy harvesting interface for battery-assisted internet of things (IoT) applications. The proposed converter is capable of harvesting energy from two photovoltaic cells and a thermoelectric generator while providing a 1.2-V regulated output and managing the battery. In addition, a negative internal voltage is produced to improve the efficiency at low input voltage. Four operating modes are employed according to the environment and loading conditions: harvesting mode (HM), storing mode (SM), boosting mode (BTM), and battery mode (BM). The simulation result shows a 87.7%, 91.9% and 93.4% peak efficiency are achieved at harvesting mode, boosting mode and battery mode, respectively.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116607859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Artificial synaptic behavior and its improvement of RRAM device with stacked solution-processed MXene layers 溶液处理MXene层堆叠RRAM器件的人工突触行为及其改进
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613944
Zongjie Shen, Chun Zhao, Yina Liu, Li Yang, Cezhou Zhao
{"title":"Artificial synaptic behavior and its improvement of RRAM device with stacked solution-processed MXene layers","authors":"Zongjie Shen, Chun Zhao, Yina Liu, Li Yang, Cezhou Zhao","doi":"10.1109/ISOCC53507.2021.9613944","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613944","url":null,"abstract":"In this work, an RRAM device with the structure of Ag/MXene/MXene/Pt was fabricated, and stacked solution-processed MXene layers acted as the resistive switching (RS) layer. The device exhibited bipolar RS performance with the operation voltage lower than 2.5 V and the switching ratio around 103. The multi-level states of conductance indicated the bionic synaptic characteristics of this device. A performance like long-term potentiation and depression (LTP/LTD) response suggested the great potential of this device in the neuromorphic system. In addition, based on the MNIST dataset, the pattern recognition system with key parameters from LTP/LTD showed the result with 85% recognition accuracy. After modulation on non-linearity of LTP and LTD curves, higher recognition accuracy was obtained, which was around 93%.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123620373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Trend of Emerging Non-Volatile Memory for AI Processor AI处理器非易失性存储器的发展趋势
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613905
L. Chang, Chenglong Li, Xin Zhao, Zixuan Zhu, Yi Tong, Shuisheng Lin, Jun Zhou
{"title":"Trend of Emerging Non-Volatile Memory for AI Processor","authors":"L. Chang, Chenglong Li, Xin Zhao, Zixuan Zhu, Yi Tong, Shuisheng Lin, Jun Zhou","doi":"10.1109/ISOCC53507.2021.9613905","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613905","url":null,"abstract":"Processing unit and memory are key components for artificial intelligent (AI) processor, which are developed by the CMOS technology and static random access memory (SRAM), respectively. As technology scaling down to sub-30 nm, the leakage current has become a critical issue to AI processor. Recently, the emerging non-volatile memory is mature gradually, such as Magnetic RAM (MRAM) and Resistive RAM (RRAM), which can be used to develop AI processor to alternate both processing unit and memory. In this work, we provide a survey on the recent tape-out work on MRAM and RRAM. We discuss the trend of MRAM and RRAM as buffer/Cache, and computingin Memory architecture. Based on the recent developments, we predict both MRAM and RRAM can be a AI product soon.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128710333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Differential Gaze Estimation with Ocular Counter-Rolling Compensation 眼球反滚动补偿的差分凝视估计
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613915
Shiwei Jin, Ji Dai, Truong Q. Nguyen
{"title":"Differential Gaze Estimation with Ocular Counter-Rolling Compensation","authors":"Shiwei Jin, Ji Dai, Truong Q. Nguyen","doi":"10.1109/ISOCC53507.2021.9613915","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613915","url":null,"abstract":"The main challenges in the gaze estimation task are the variations in head poses, eye shapes and inner eye structures amongst individuals. Conventional methods have proposed many techniques to reduce these variations. One of the most adopted techniques is the normalization method which realigns the head pose to remove the roll component of head pose. However, this global transformation, which forces the eye to move with the other part of the face together, violates the human anatomy as eyeballs are controlled separately by the surrounding muscles. These muscles restrain the eyeball to be horizontally stable even when the head is tilted in a natural pose. In this work, we propose a novel method to model this counter-rolling effect and use it to remove the error from the normalization step. Experiments validate our approach, which outperforms state-of-the-art eye-image-only gaze estimation methods.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129416793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
FPGA Design Duplication based on the Bitstream Extraction 基于比特流提取的FPGA复制设计
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613991
Soyeon Choi, Nari Im, Hoyoung Yoo
{"title":"FPGA Design Duplication based on the Bitstream Extraction","authors":"Soyeon Choi, Nari Im, Hoyoung Yoo","doi":"10.1109/ISOCC53507.2021.9613991","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613991","url":null,"abstract":"Due to fast design process, SRAM-based Field Programmable Gate Array (FPGA) is widely used for various industrial applications. Since the netlist stored in external nonvolatile memory is transferred in the form of bitstream whenever FPGA powers on, the netlist on FPGA is vulnerable for malicious attacks. In this paper, we present how the attackers duplicate the original FPGA design using FPGA bitstream extraction, and emphasize the need for countermeasure to prevent such malicious duplication. Xilinx Spartan-6 evaluation board is used, which includes XC6SLX9 FPGA and XCF04S flash memory. According to the experiments, the described method is succeeded in replicating the original design on the other FPGA.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129632093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 6b 48-GS/s Asynchronous 2b/cycle Time-Interleaved ADC in 28-nm CMOS 基于28nm CMOS的6b 48gs /s异步2b/周期时间交错ADC
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613967
Hong-Seok Choi, Seungha Roh, Sanghee Lee, Jungjune Park, Kwang-Hoon Lee, Young-Ha Hwang, D. Jeong
{"title":"A 6b 48-GS/s Asynchronous 2b/cycle Time-Interleaved ADC in 28-nm CMOS","authors":"Hong-Seok Choi, Seungha Roh, Sanghee Lee, Jungjune Park, Kwang-Hoon Lee, Young-Ha Hwang, D. Jeong","doi":"10.1109/ISOCC53507.2021.9613967","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613967","url":null,"abstract":"This brief presents a 32-way 6b 48-GS/s asynchronous time-interleaved ADC. To enhance sub-ADC conversion speed, 2b/cycle asynchronous SAR ADC is adopted for sub-ADC structure, which can operate at 1.5-GHz. Instead of using reference DAC, 9 built-in reference samplers are employed for 6b 2b/cycle operation. Interleaver incorporates 8 sample and hold amplifiers (SHA) and each SHA drives 4 sub-ADCs. Core ADC uses 1 V supply and the interleaver uses 1.1V supply to secure the linearity of the switches. The proposed time-interleaved ADC has been fabricated in 28-nm CMOS technology and occupies an active area of 0.3565 mm2. The ADC consumes 72.3mW at the sampling rate of 48 GS/s, including clock distribution power.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129827118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Maximum Eye Tracking Clock-and-Data Recovery Scheme with Golden Section Search(GSS) Algorithm in 28-nm CMOS 基于黄金分割搜索(GSS)算法的28纳米CMOS最大眼动追踪时钟和数据恢复方案
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613919
Seungha Roh, Moon-Chul Choi, D. Jeong
{"title":"A Maximum Eye Tracking Clock-and-Data Recovery Scheme with Golden Section Search(GSS) Algorithm in 28-nm CMOS","authors":"Seungha Roh, Moon-Chul Choi, D. Jeong","doi":"10.1109/ISOCC53507.2021.9613919","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613919","url":null,"abstract":"This paper presents a 2x-oversampling clock-and-data recovery (CDR) scheme with a golden section search (GSS) algorithm [1] of a 32 Gb/s non-return-to-zero (NRZ) receiver. The proposed CDR with GSS adaptively selects the optimum sampling phase of data clock as well as recovering edge clock. It operates fast without requiring slow procedures such as the BER measurement. To control sampling phases of edge clock and data clock, two parallel phase interpolators (PI) are used. After 2x-oversampling CDR locks, phase difference between edge and data clock is adaptively adjusted by the GSS algorithm. Assuming an eye height is a convex function in a 1 unit-interval, the GSS adaptation offers faster convergence than other search adaptation algorithms.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128994360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Understanding and Reducing Weight-Load Overhead of Systolic Deep Learning Accelerators
2021 18th International SoC Design Conference (ISOCC) Pub Date : 2021-10-06 DOI: 10.1109/ISOCC53507.2021.9613929
Jin-Gul Joo, Minyong Yoon, Jungwook Choi, Mingu Kang, Jong-Geon Lee, J. So, Il-Kwon Yun, Yongsuk Kwon, KyungSoo Kim
{"title":"Understanding and Reducing Weight-Load Overhead of Systolic Deep Learning Accelerators","authors":"Jin-Gul Joo, Minyong Yoon, Jungwook Choi, Mingu Kang, Jong-Geon Lee, J. So, Il-Kwon Yun, Yongsuk Kwon, KyungSoo Kim","doi":"10.1109/ISOCC53507.2021.9613929","DOIUrl":"https://doi.org/10.1109/ISOCC53507.2021.9613929","url":null,"abstract":"As an energy-efficient computing engine for deep neural network inference, 2D systolic array architectures have been widely adopted in modern deep learning accelerators. However, despite high compute density and energy-efficient data passing, systolic accelerators suffer a non-trivial overhead of loading data stationed inside their local register file. This loading overhead becomes a critical issue when a frequent reload of stationary data (e.g., weight parameters) is required. This paper proposes a simple yet practical SW-HW co-optimization that reverses the weight-load order and adds a dedicated path for weight-load. On diverse deep learning applications, the proposed method reduces the weight-load overhead and achieves up to 1.8× speedup with 40% energy savings.","PeriodicalId":185992,"journal":{"name":"2021 18th International SoC Design Conference (ISOCC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125870606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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