ChaCha20-Poly1305 Crypto Core Compatible with Transport Layer Security 1.3

Abstract

The security of the information represents a vital part of all communications protocols. In computer networks, Transport Layer Security (TLS) represents the majority of the use of secure channels for end-to-end communications. However, the efforts are directed only to optimize the software implementations. This paper shows an Authenticated Encryption with Associated Data (AEAD) hardware implementation of ChaCha20-Poly1305 compatible with TLS 1.3. Compared to a software implementation in a RISC-V environment, the performance increase by 7. The AEAD implementation reaches a speed of 21.5-cycle/byte.×The design is implemented in Xilinx Virtex-7 XC7VX485T Field-Programmable Gate Array (FPGA), using 7897 Look-Up Tables (LUT) and 4840 Flip-Flops (FF), represented in 26% of ChaCha20 and 54% of Poly1305.