发布求助
文献互助 智能选刊 最新文献

The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.最新文献

筛选
英文 中文
A switched-voltage high-accuracy sample/hold circuit 一个开关电压高精度采样/保持电路
The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04. Pub Date : 2006-12-01 DOI: 10.1109/APCCAS.2006.342342
K. Ohno, H. Matsumoto, K. Murao
{"title":"A switched-voltage high-accuracy sample/hold circuit","authors":"K. Ohno, H. Matsumoto, K. Murao","doi":"10.1109/APCCAS.2006.342342","DOIUrl":"https://doi.org/10.1109/APCCAS.2006.342342","url":null,"abstract":"In this paper, three switched-voltage (SV) sample/hold (S/H) circuits are presented to compensate for clock-feed-through (CFT) and channel-length modulation effect. They consist of a CMOS SV-delay cell. Thus, the configuration is very simple. The proposed circuits can be operated using simple nonoverlapping two phase clocks. The performance is verified by simulations on PSpice.","PeriodicalId":185817,"journal":{"name":"The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126325331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Area efficient architecture for the embedded block coding in JPEG 2000 JPEG 2000中嵌入式块编码的区域高效结构
The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04. Pub Date : 2005-11-01 DOI: 10.1109/ASSCC.2005.251791
Hung-Chi Fang, Yu-Wei Chang, Liang-Gee Chen
{"title":"Area efficient architecture for the embedded block coding in JPEG 2000","authors":"Hung-Chi Fang, Yu-Wei Chang, Liang-Gee Chen","doi":"10.1109/ASSCC.2005.251791","DOIUrl":"https://doi.org/10.1109/ASSCC.2005.251791","url":null,"abstract":"An area efficient architecture for the embedded block coding is presented in this paper. A new algorithm is proposed to compute the state variables on-the-fly. Thus, the memory for the state variables are eliminated, which occupies more than 60% area in a conventional embedded block coding architecture. The area of the proposed architecture is only 1/6 of conventional architectures while the throughput is the same as others. The proposed architecture has the highest performance comparing with other existing architectures according to the experimental results.","PeriodicalId":185817,"journal":{"name":"The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122622131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Variable fractional-delay filter design using weighted-least-squares singular-value decomposition 基于加权最小二乘奇异值分解的可变分数延迟滤波器设计
The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04. Pub Date : 2004-11-21 DOI: 10.1109/TENCON.2004.1414352
T. Deng
{"title":"Variable fractional-delay filter design using weighted-least-squares singular-value decomposition","authors":"T. Deng","doi":"10.1109/TENCON.2004.1414352","DOIUrl":"https://doi.org/10.1109/TENCON.2004.1414352","url":null,"abstract":"This paper proposes a weighted-least-squares singular-value-decomposition (WLS-SVD) method and shows that the problem of designing 1D variable fractional-delay (VFD) digital filter can be elegantly reduced to the easier sub-problems that involve 1D constant filter designs and 1D polynomial approximations. By utilizing the WLS-SVD of the variable design specification, we prove that both 1D constant filters and 1D polynomials possess either symmetry or antisymmetry simultaneously. Therefore, a VFD filter can be efficiently obtained by designing 1D constant filters with symmetric or antisymmetric coefficients and performing 1D symmetric or antisymmetric polynomial approximations. Our computer simulations have shown that the WLS-SVD design can achieve much higher design accuracy with significantly reduced filter complexity than the existing WLS design method.","PeriodicalId":185817,"journal":{"name":"The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123585575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low-complexity architecture of inverse fast Fourier transform for XDS 面向XDS的低复杂度快速傅里叶反变换体系结构
The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04. Pub Date : 2004-07-25 DOI: 10.1109/MWSCAS.2004.1354107
Hsin-Horng Chen, O. Chen, Heng-Cheng Yeh, Cheng-Shing Wu
{"title":"A low-complexity architecture of inverse fast Fourier transform for XDS","authors":"Hsin-Horng Chen, O. Chen, Heng-Cheng Yeh, Cheng-Shing Wu","doi":"10.1109/MWSCAS.2004.1354107","DOIUrl":"https://doi.org/10.1109/MWSCAS.2004.1354107","url":null,"abstract":"In this work, a low-complexity architecture of the inverse fast Fourier transform (IFFT) using the serial-input-parallel-output data flow is designed for digital subscriber line for any class (XDSL). Since input data in the XDSL are symmetric, the computation of the IFFT can be reduced to multiplication accumulation operations in the real part. Furthermore, consideration is taken to process all multiplication operations together to lower hardware complexity. By separating all multiplication and accumulation operations into two groups, only an interface is needed to be the bridge between the two. The coefficients of the IFFT are represented by the canonic signed digits (CSDs) so that their shared terms are derived to reduce the number of adders for accomplishing multiplication operations. By using multiplexors to do the interface, the computation results from the multiplication part are distributed to their corresponding accumulators according to a time sequence. In addition, the size of the word length can be adequately selected to match the required signal-to-noise ratio (SNR). As compared to the conventional IFFT architectures, the proposed IFFT architecture can have the least hardware complexity at the same throughput rate and SNR performance.","PeriodicalId":185817,"journal":{"name":"The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123151973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Simultaneous stabilization of nD system via local-global principle 基于局部-全局原理的nD系统的同时镇定
The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04. Pub Date : 2004-07-25 DOI: 10.1109/MWSCAS.2004.1354217
K. Mori
{"title":"Simultaneous stabilization of nD system via local-global principle","authors":"K. Mori","doi":"10.1109/MWSCAS.2004.1354217","DOIUrl":"https://doi.org/10.1109/MWSCAS.2004.1354217","url":null,"abstract":"This paper addresses the relationship between the simultaneous stabilizability and the strong stabilizability of the multidimensional system. We present that the simultaneous stabilizability over a commutative ring cannot be given by the simultaneous stabilizability over its local rings in general. But if we have one-side coprime factorization, we show that solving the simultaneous stabilizability of the multidimensional system can be recast as solving the strong stabilizability of the multidimensional system. We consider the structural stability.","PeriodicalId":185817,"journal":{"name":"The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121809504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A high-speed high-resolution comparator 高速高分辨率比较器
The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04. Pub Date : 2004-07-25 DOI: 10.1109/MWSCAS.2004.1353902
M. Banihashemi
{"title":"A high-speed high-resolution comparator","authors":"M. Banihashemi","doi":"10.1109/MWSCAS.2004.1353902","DOIUrl":"https://doi.org/10.1109/MWSCAS.2004.1353902","url":null,"abstract":"This paper describes a comparator that not only eliminates offset cancellation capacitors from the signal path in preamplification and latch modes, but also incorporates open loop offset cancellation to cancel the offset of both preamplification stages and the latch. This new architecture effectively increases both speed and resolution. By applying offset cancellation, an offset of less than 800 /spl mu/V at comparison rate of 300 MHz with a 6 mW power dissipation and 3 V power supply has been achieved. The comparator has been extracted and simulated with a 0.35 /spl mu/m HSPICE model.","PeriodicalId":185817,"journal":{"name":"The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117166026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Bit-rate maximization for multiuser OFDM systems 多用户OFDM系统的比特率最大化
The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04. Pub Date : 2004-07-25 DOI: 10.1109/MWSCAS.2004.1354336
H. Tase, S. Ohno, Y. Otani, T. Hinamoto
{"title":"Bit-rate maximization for multiuser OFDM systems","authors":"H. Tase, S. Ohno, Y. Otani, T. Hinamoto","doi":"10.1109/MWSCAS.2004.1354336","DOIUrl":"https://doi.org/10.1109/MWSCAS.2004.1354336","url":null,"abstract":"OFDM (orthogonal frequency division multiplexing) is one of next-generation modulation techniques, which achieves high bandwidth efficiency and is robust to frequency selective fading. Bit-rate and bit error rate can be improved by utilizing adaptive modulation scheme on each subcarrier. Multiplexing is also possible by allocating subcarriers to multiple users. Since users have different channels, the quality of OFDM-based multiplexing systems depends on the subcarrier allocation. In this paper, we consider a subcarrier allocation and adaptive modulation for a multiuser OFDM system. We impose a transmission power constraint on each user to achieve a fair resource allocation. Under this condition, we propose a method to maximize the sum of each user's bit-rate. The effectiveness of the proposed method is numerically evaluated by simulation examples.","PeriodicalId":185817,"journal":{"name":"The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.","volume":"242 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123743874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Analog circuit optimizer based on computational intelligence techniques 基于计算智能技术的模拟电路优化器
The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04. Pub Date : 2004-07-25 DOI: 10.1109/MWSCAS.2004.1354351
K. Prakobwaitayakit
{"title":"Analog circuit optimizer based on computational intelligence techniques","authors":"K. Prakobwaitayakit","doi":"10.1109/MWSCAS.2004.1354351","DOIUrl":"https://doi.org/10.1109/MWSCAS.2004.1354351","url":null,"abstract":"The computational intelligence techniques for analog circuit optimizer are presented in this paper. This technique uses a diffusion genetic algorithm (DGA) to identify multiple \"good\" solutions from a multiobjective fitness landscape which are tuned using a local hill-climbing algorithm. The DGA together with fast and accurate circuit performance estimator (CPE) based on neuro-computing technology is used to provide a nature niching mechanism that has considerable computational advantages and generate as many \"good\" design solutions as possible. The local hill-climbing algorithm restricts the search in the basin of attraction of a design solution, thus tries to tune the design up-to the sub-optimum by using SPICE to validated the performance parameters of synthesized circuits.","PeriodicalId":185817,"journal":{"name":"The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.","volume":"28 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116405357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Feedback-loop computer aided design for PWM DC-DC converters operated in continuous conduction mode and its application for a buck converter 连续导通模式下PWM DC-DC变换器的反馈回路计算机辅助设计及其在降压变换器中的应用
The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04. Pub Date : 2004-07-25 DOI: 10.1109/MWSCAS.2004.1354349
F. Grasso, A. Reatti
{"title":"Feedback-loop computer aided design for PWM DC-DC converters operated in continuous conduction mode and its application for a buck converter","authors":"F. Grasso, A. Reatti","doi":"10.1109/MWSCAS.2004.1354349","DOIUrl":"https://doi.org/10.1109/MWSCAS.2004.1354349","url":null,"abstract":"Dc and small-signal circuit models for the PWM buck converter operated in the continuous conduction mode (CCM) are given and applied to a buck converter. The model taking into account the parasitic components, such as the equivalent series resistance (ESR) of the filter inductor, the ESR of the filter capacitor, the transistor on-resistance, and the diode forward resistance and offset voltage. The dc voltage transfer function, the control-to-output transfer function, the input and the output impedance are automatically derived and plotted by means of a dedicated computer program. The main advantage of the proposed method is the application of a linear equivalent circuit of the converter considering the overall parasitic component to a simulation program, so that the feedback-loop is accurately designed with a computer aid.","PeriodicalId":185817,"journal":{"name":"The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122531710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An adaptive current-to-voltage converter for sensor applications 用于传感器应用的自适应电流-电压转换器
The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04. Pub Date : 2004-07-25 DOI: 10.1109/MWSCAS.2004.1354371
Chunyan Wang
{"title":"An adaptive current-to-voltage converter for sensor applications","authors":"Chunyan Wang","doi":"10.1109/MWSCAS.2004.1354371","DOIUrl":"https://doi.org/10.1109/MWSCAS.2004.1354371","url":null,"abstract":"Aiming at the needs of high sensitivity and wide dynamic range in many sensor applications, we present, in this paper, a structure of current-to-voltage conversion circuit. It is made to be very sensitive to a very weak current signal and to be able to lower its conversion gain if the signal becomes stronger. The variable conversion gain is obtained using the non-linearity of the MOS transistor characteristics. This circuit is designed to use the resistive features of the devices, instead of the transconductances. The circuit consists of only four transistors and can be fabricated in a single poly process.","PeriodicalId":185817,"journal":{"name":"The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122883184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信