A low-complexity architecture of inverse fast Fourier transform for XDS

Abstract

In this work, a low-complexity architecture of the inverse fast Fourier transform (IFFT) using the serial-input-parallel-output data flow is designed for digital subscriber line for any class (XDSL). Since input data in the XDSL are symmetric, the computation of the IFFT can be reduced to multiplication accumulation operations in the real part. Furthermore, consideration is taken to process all multiplication operations together to lower hardware complexity. By separating all multiplication and accumulation operations into two groups, only an interface is needed to be the bridge between the two. The coefficients of the IFFT are represented by the canonic signed digits (CSDs) so that their shared terms are derived to reduce the number of adders for accomplishing multiplication operations. By using multiplexors to do the interface, the computation results from the multiplication part are distributed to their corresponding accumulators according to a time sequence. In addition, the size of the word length can be adequately selected to match the required signal-to-noise ratio (SNR). As compared to the conventional IFFT architectures, the proposed IFFT architecture can have the least hardware complexity at the same throughput rate and SNR performance.