一个开关电压高精度采样/保持电路

The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04. Pub Date : 2006-12-01 DOI:10.1109/APCCAS.2006.342342

K. Ohno, H. Matsumoto, K. Murao

{"title":"一个开关电压高精度采样/保持电路","authors":"K. Ohno, H. Matsumoto, K. Murao","doi":"10.1109/APCCAS.2006.342342","DOIUrl":null,"url":null,"abstract":"In this paper, three switched-voltage (SV) sample/hold (S/H) circuits are presented to compensate for clock-feed-through (CFT) and channel-length modulation effect. They consist of a CMOS SV-delay cell. Thus, the configuration is very simple. The proposed circuits can be operated using simple nonoverlapping two phase clocks. The performance is verified by simulations on PSpice.","PeriodicalId":185817,"journal":{"name":"The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.","volume":"59 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A switched-voltage high-accuracy sample/hold circuit\",\"authors\":\"K. Ohno, H. Matsumoto, K. Murao\",\"doi\":\"10.1109/APCCAS.2006.342342\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, three switched-voltage (SV) sample/hold (S/H) circuits are presented to compensate for clock-feed-through (CFT) and channel-length modulation effect. They consist of a CMOS SV-delay cell. Thus, the configuration is very simple. The proposed circuits can be operated using simple nonoverlapping two phase clocks. The performance is verified by simulations on PSpice.\",\"PeriodicalId\":185817,\"journal\":{\"name\":\"The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.\",\"volume\":\"59 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCCAS.2006.342342\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.2006.342342","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

本文提出了三种开关电压(SV)采样/保持(S/H)电路来补偿时钟馈通(CFT)和信道长度调制效应。它们由CMOS sv延迟单元组成。因此，配置非常简单。所提出的电路可以使用简单的非重叠两相时钟进行操作。通过PSpice仿真验证了该算法的性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A switched-voltage high-accuracy sample/hold circuit

In this paper, three switched-voltage (SV) sample/hold (S/H) circuits are presented to compensate for clock-feed-through (CFT) and channel-length modulation effect. They consist of a CMOS SV-delay cell. Thus, the configuration is very simple. The proposed circuits can be operated using simple nonoverlapping two phase clocks. The performance is verified by simulations on PSpice.

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The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.

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