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2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)最新文献

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Constrained signal selection for post-silicon validation 后硅验证的约束信号选择
2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2012-11-01 DOI: 10.1109/HLDVT.2012.6418245
K. Basu, P. Mishra, Priyadarsan Patra
{"title":"Constrained signal selection for post-silicon validation","authors":"K. Basu, P. Mishra, Priyadarsan Patra","doi":"10.1109/HLDVT.2012.6418245","DOIUrl":"https://doi.org/10.1109/HLDVT.2012.6418245","url":null,"abstract":"Limited signal observability is a major concern during post-silicon validation. On-chip trace buffers store a small number of signal states every cycle. Existing signal selection techniques are designed to select a set of signals based on the trace buffer width. In a real-life scenario, it is reasonable that a designer has determined some important signals that must be traced. In this paper, we study the constrained signal selection problem where a set of trace signals are already provided by the designer and the remaining signals have to be determined to improve overall restoration performance. Our experimental results using ISCAS'89 benchmarks demonstrate that up to 5% improvement can be obtained in restoration performance compared to existing approaches.","PeriodicalId":184509,"journal":{"name":"2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130838250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Accelerating SystemC simulations using GPUs 使用gpu加速系统模拟
2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2012-11-01 DOI: 10.1109/HLDVT.2012.6418255
M. Nanjundappa, A. Kaushik, Hiren D. Patel, S. Shukla
{"title":"Accelerating SystemC simulations using GPUs","authors":"M. Nanjundappa, A. Kaushik, Hiren D. Patel, S. Shukla","doi":"10.1109/HLDVT.2012.6418255","DOIUrl":"https://doi.org/10.1109/HLDVT.2012.6418255","url":null,"abstract":"Recent developments in graphics processing unit (GPU) technology has invigorated an interest in using GPUs for accelerating the simulation of SystemC models. SystemC is extensively used for design space exploration, and early performance analysis of hardware systems. SystemC's reference implementation of the simulation kernel supports a single-threaded simulation kernel. However, modern computing platforms offer substantially more compute power by means of multiple central processing units, and multiple co-processors such as GPUs. This has peaked an interest in parallelizing SystemC simulations. Of these, several efforts focus on utilizing the massive parallelism offered by GPUs as an alternate computing platform. In this paper, we present a summary of these recent research efforts that propose using GPUs for accelerating SystemC simulation.","PeriodicalId":184509,"journal":{"name":"2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115253457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Automatic generation of Verilog bus transactors from natural language protocol specifications Verilog总线事务从自然语言协议规范的自动生成
2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2012-11-01 DOI: 10.1109/HLDVT.2012.6418240
I. Harris
{"title":"Automatic generation of Verilog bus transactors from natural language protocol specifications","authors":"I. Harris","doi":"10.1109/HLDVT.2012.6418240","DOIUrl":"https://doi.org/10.1109/HLDVT.2012.6418240","url":null,"abstract":"We present an approach to analyze natural language protocol specifications to generate Verilog bus transactors. We present a set of transaction concepts which are used, in text and formal models, to describe the behavior of transactions in a protocol. We employ semantic parsing to identify these transaction concepts in the natural language specification. The transaction concepts are translated into Verilog constructs to define Verilog tasks which model bus transactions defined in the protocol.","PeriodicalId":184509,"journal":{"name":"2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126780125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The strange pair: IP-XACT and univerCM to integrate heterogeneous embedded systems 奇怪的一对:IP-XACT和univerCM集成异构嵌入式系统
2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2012-11-01 DOI: 10.1109/HLDVT.2012.6418246
Diego Braga, F. Fummi, G. Pravadelli, S. Vinco
{"title":"The strange pair: IP-XACT and univerCM to integrate heterogeneous embedded systems","authors":"Diego Braga, F. Fummi, G. Pravadelli, S. Vinco","doi":"10.1109/HLDVT.2012.6418246","DOIUrl":"https://doi.org/10.1109/HLDVT.2012.6418246","url":null,"abstract":"Modern embedded systems require a tight integration among several heterogeneous components including digital and analog HW, as well as HW-dependent SW. In literature there is a lack of a complete approach, allowing reuse and at the same time supporting correct integration of heterogeneous components. Indeed, traditional approaches rely either on homogeneous top-down methodologies (that do not allow reuse) or on co-simulation (that does not guarantee correct integration). This paper proposes to combine IP-XACT and UNIVERCM. The former is an IEEE standard for specifying interface and communication style of digital IPs. The latter is a computational model that allows to represent the starting heterogeneous components in a homogeneous way. In this way, IP-XACT is used in this paper to support the integration of general heterogeneous components, to extract component interfaces and to generate the necessary connecting modules. Furthermore, UNIVERCM allows to generate a homogeneous representation of the components behavior (in a bottom-up flow) to allow simulation and validation of the generated components and of the final system. Thus, this strange pair allows integration and validation of system communication. The effectiveness of this novel approach has been proven on complex heterogeneous benchmarks.","PeriodicalId":184509,"journal":{"name":"2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115728778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Cause and effect of nondeterministic behavior in sequential and parallel SystemC simulators 顺序和并行SystemC模拟器中不确定性行为的原因和影响
2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2012-11-01 DOI: 10.1109/HLDVT.2012.6418254
Christoph Schumacher, Jan Weinstock, R. Leupers, G. Ascheid
{"title":"Cause and effect of nondeterministic behavior in sequential and parallel SystemC simulators","authors":"Christoph Schumacher, Jan Weinstock, R. Leupers, G. Ascheid","doi":"10.1109/HLDVT.2012.6418254","DOIUrl":"https://doi.org/10.1109/HLDVT.2012.6418254","url":null,"abstract":"Simulators are used to aid the design of computer systems. Together with the computational power of computer systems, the demands towards their simulators are growing regarding speed, flexibility, as well as the predictability of their behavior. To increase simulation speed, simulation models are abstracted and simulated in parallel. To reduce simulator development time and to provide the greatest possible modeling flexibility, SystemC allows models to be written using C++ without restrictions. All three means, especially when used in combination, also increase the difficulty to reason about the behavior of the resulting simulator, in the worst case leading to unpredictable simulation behavior. This may threaten the fitness of simulators for demanding use-cases like the debugging of race conditions. This work discusses likely causes and impact of nondeterministic simulator behavior. Three examples taken from real-life models are used to illustrate the matter.","PeriodicalId":184509,"journal":{"name":"2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116937662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Using decision diagrams to compactly represent the state space for explicit model checking 使用决策图紧凑地表示状态空间，以便进行显式模型检查
2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2012-11-01 DOI: 10.1109/HLDVT.2012.6418238
Hao Zheng, Andrew Price, C. Myers
{"title":"Using decision diagrams to compactly represent the state space for explicit model checking","authors":"Hao Zheng, Andrew Price, C. Myers","doi":"10.1109/HLDVT.2012.6418238","DOIUrl":"https://doi.org/10.1109/HLDVT.2012.6418238","url":null,"abstract":"The enormous number of states reachable during explicit model checking is the main bottleneck for scalability. This paper presents approaches of using decision diagrams to represent very large state space compactly and efficiently. This is possible for asynchronous systems as two system states connected by a transition often share many same local portions. Using decision diagrams can significantly reduce memory demand by not using memory to store the redundant information among different states. This paper considers multi-value decision diagrams for this purpose. Additionally, a technique to reduce the runtime overhead of using these diagrams is also described. Experimental results and comparison with the state compression method as implemented in the model checker SPIN show that the approaches presented in this paper are memory efficient for storing large state space with acceptable runtime overhead.","PeriodicalId":184509,"journal":{"name":"2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132340878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A formal method to improve SystemVerilog functional coverage 改进SystemVerilog功能覆盖的正式方法
2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2012-11-01 DOI: 10.1109/HLDVT.2012.6418243
An-Che Cheng, Chia-Chih Yen, Jing-Yang Jou
{"title":"A formal method to improve SystemVerilog functional coverage","authors":"An-Che Cheng, Chia-Chih Yen, Jing-Yang Jou","doi":"10.1109/HLDVT.2012.6418243","DOIUrl":"https://doi.org/10.1109/HLDVT.2012.6418243","url":null,"abstract":"Improving functional coverage efficiently in a verification environment based on constrained random simulation could be a difficult task, since some design states are hard to be reached by random input patterns. On the other hand, manually crafting direct test patterns may be time consuming. In this paper, a functional test pattern generation (FTPG) framework is proposed to automatically produce deterministic test patterns for complete coverage. The framework is based on the functional coverage model (covergroup) provided by SystemVerilog, and it could be easily integrated to modern digital design flow. We synthesize a practical subset of covergroup language constructs to enable FTPG by a SAT-solver. An algorithm called MRRS is proposed to minimize the potential large complexity of the synthesized circuits. Preliminary experimental results demonstrate that MRRS could facilitate FTPG to achieve 43X speed-up in average while the maximum speed-up can reach 67X. To the best of our knowledge, this is the first paper which proposes an FTPG method that utilizes covergroups.","PeriodicalId":184509,"journal":{"name":"2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121807222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Using haloes in mixed-signal assertion based verification 在基于混合信号断言的验证中使用光晕
2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2012-11-01 DOI: 10.1109/HLDVT.2012.6418242
Dogan Ulus, A. Sen
{"title":"Using haloes in mixed-signal assertion based verification","authors":"Dogan Ulus, A. Sen","doi":"10.1109/HLDVT.2012.6418242","DOIUrl":"https://doi.org/10.1109/HLDVT.2012.6418242","url":null,"abstract":"We develop an assertion based verification solution for analog mixed-signal designs. We introduce the halo concept for analog signals to express them with their tolerance and variation values in assertions. The halo of a signal provides a relaxation over the signal and it defines an effective region for that signal which can be used in assertion based verification. Using haloes for analog signals allow us to define a new set of comparison relations between two analog signals including their equivalence. In our intended design flow, these new analog signal operators are placed into the Analog layer of mixed-signal assertion languages as an extension. We present experimental results on a programmable switch and a VCO.","PeriodicalId":184509,"journal":{"name":"2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121896301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
On-chip stimuli generation for post-silicon validation 芯片上刺激生成后硅验证
2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2012-11-01 DOI: 10.1109/HLDVT.2012.6418251
N. Nicolici
{"title":"On-chip stimuli generation for post-silicon validation","authors":"N. Nicolici","doi":"10.1109/HLDVT.2012.6418251","DOIUrl":"https://doi.org/10.1109/HLDVT.2012.6418251","url":null,"abstract":"In contrast to pre-silicon verification environments, insystem validation is not strongly constrained by the number of stimuli that can be applied; rather, the quality of the patterns, as well as the observation of the events of interest are the real concern. This paper motivates the need for developing structured methods for porting the controllability aspects of pre-silicon verification into post-silicon validation environments. Use cases and challenges for such methods are outlined.","PeriodicalId":184509,"journal":{"name":"2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117226160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Embedded system verification through constraint-based scheduling 基于约束调度的嵌入式系统验证
2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2012-11-01 DOI: 10.1109/HLDVT.2012.6418248
O. El-Mahi, G. Pesant, G. Nicolescu, G. Beltrame
{"title":"Embedded system verification through constraint-based scheduling","authors":"O. El-Mahi, G. Pesant, G. Nicolescu, G. Beltrame","doi":"10.1109/HLDVT.2012.6418248","DOIUrl":"https://doi.org/10.1109/HLDVT.2012.6418248","url":null,"abstract":"Multiprocessor System-on-Chip (MPSoC) verification has become one of the main bottlenecks in the design process of embedded systems. Proving the correctness of a design efficiently is of extreme importance to reduce cost and time-to-market. Simulation is a common verification method, but complex systems usually require long simulation times. This work introduces Constraint Programming (CP) as a powerful tool for the verification of performance metrics of MPSoCs. Our methodology was evaluated using streaming applications mapped onto a target MPSoC. The resulting constraint-based scheduling problem allowed us to identify performance constraint violations in a fraction of the time required by simulation-based verification.","PeriodicalId":184509,"journal":{"name":"2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"2007 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125616901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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