{"title":"A functional test generation technique for RTL datapaths","authors":"B. Alizadeh, M. Fujita","doi":"10.1109/HLDVT.2012.6418244","DOIUrl":"https://doi.org/10.1109/HLDVT.2012.6418244","url":null,"abstract":"This paper presents an automatic test pattern generation (ATPG) technique applicable to register transfer level (RTL) datapath circuits which are usually very hard-to-test due to the presence of complex loop structures. Although to achieve high fault coverage it is essential to symbolically simulate all possible execution paths, we have come up with a case splitting mechanism which makes use of path sensitization information from the faulty location to primary outputs so that the size of formulae to be solved is significantly reduced. Experimental results show robustness and reliability of our method compared to the state-of-the-art RTL ATPG techniques. In addition, the results indicate that, in comparison with [8], with case splitting the ATPG time has been reduced by 22%-41%.","PeriodicalId":184509,"journal":{"name":"2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114722868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Monitoring distributed reactive systems","authors":"Yu Bai, J. Brandt, K. Schneider","doi":"10.1109/HLDVT.2012.6418247","DOIUrl":"https://doi.org/10.1109/HLDVT.2012.6418247","url":null,"abstract":"Recent results on the desynchronization of synchronous systems introduced the subclass of so-called endo/isochronous systems. Since the modules of these systems can derive their own local clocks from their inputs, they can be implemented as asynchronous components without inefficient synchronizations. Runtime verification has a similar problem since one has to add a monitor to an existing system where typically a synchronous composition is assumed. In this paper, we therefore propose to use the endo/isochronous system theory to implement asynchronous monitors that are still able to check the original synchronous behavior. We only demand that the entire system obtained by adding the monitor is an endo/isochronous system so that we can implement a suitable wrapper around the monitor (and the other components). For the implementation, we use heuristics to check endochrony like the sequentiality of the implemented functions.","PeriodicalId":184509,"journal":{"name":"2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132284266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"ToucHMore toolchain and system software for energy and variability customisation","authors":"N. Audsley, Ian Gray, A. Acquaviva, Ralph Haines","doi":"10.1109/HLDVT.2012.6418257","DOIUrl":"https://doi.org/10.1109/HLDVT.2012.6418257","url":null,"abstract":"Run-time platform variability presents a number of challenges to the system software in order that a run-time environment is presented to applications that sufficiently masks dynamic platform variability (including fabrication variability), whilst allowing applications to tune overall system performance to exploit key aspects of dynamic energy usage and platform variability. The approach taken within the Touchmore project is to model key aspects of the platform in order that performance and variability can be understood and exploited by the system software. In turn, the system software (comprising OS and run-time) utilises the model so that aspects of variability and energy usage are abstracted from the platform, then monitored and controlled in order to meet policy goals, eg. energy minimisation. This paper documents aspects of the modeling and system software structure to show how the Touchmore project is managing energy and platform variability using customisation of the application, system software and toolchain.","PeriodicalId":184509,"journal":{"name":"2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116956727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Generating formal system models from natural language descriptions","authors":"R. Drechsler, I. Harris, R. Wille","doi":"10.1109/HLDVT.2012.6418259","DOIUrl":"https://doi.org/10.1109/HLDVT.2012.6418259","url":null,"abstract":"The initial starting point of each design process usually is given by means of a textual specification provided in a natural language. However, the process of creating an accurate and complete formal representation has always been a bottleneck in the design. Manually generating such a formal description from the specification is expensive, requires significant time, and a large number of well-trained design and verification engineers. Usually, only humans with expert design knowledge are assumed to have the ability to properly interpret the respective specification documents.","PeriodicalId":184509,"journal":{"name":"2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125945614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}