2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)

Single-source hardware modeling of different abstraction levels with State Charts

Pub Date : 2012-11-01 DOI: 10.1109/HLDVT.2012.6418241 Rainer Findenig, T. Leitner, W. Ecker

Behavior Driven Development for circuit design and verification

Pub Date : 2012-11-01 DOI: 10.1109/HLDVT.2012.6418237 Melanie Diepenbeck, Mathias Soeken, Daniel Große, R. Drechsler

Automatic generation of deadlock detection algorithms for a family of microarchitecture description languages of communication fabrics

Pub Date : 2012-11-01 DOI: 10.1109/HLDVT.2012.6418239 Freek Verbeek, J. Schmaltz