2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)最新文献

Single-source hardware modeling of different abstraction levels with State Charts 使用状态图对不同抽象级别进行单源硬件建模

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2012-11-01 DOI: 10.1109/HLDVT.2012.6418241

Rainer Findenig, T. Leitner, W. Ecker

引用次数: 1

Behavior Driven Development for circuit design and verification 行为驱动开发电路设计和验证

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2012-11-01 DOI: 10.1109/HLDVT.2012.6418237

Melanie Diepenbeck, Mathias Soeken, Daniel Große, R. Drechsler

引用次数: 25

Automatic generation of deadlock detection algorithms for a family of microarchitecture description languages of communication fabrics 一种通信结构微结构描述语言的死锁检测算法的自动生成

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2012-11-01 DOI: 10.1109/HLDVT.2012.6418239

Freek Verbeek, J. Schmaltz

{"title":"Automatic generation of deadlock detection algorithms for a family of microarchitecture description languages of communication fabrics","authors":"Freek Verbeek, J. Schmaltz","doi":"10.1109/HLDVT.2012.6418239","DOIUrl":"https://doi.org/10.1109/HLDVT.2012.6418239","url":null,"abstract":"In the multi-core era, ensuring deadlock freedom of communication fabrics is an important challenge. Intel proposed xMAS, a microarchitecture description language (MaDL), to support the formal modelling and verification of communication fabrics. The xMAS language is restricted to eight basic primitives. Using this restriction, an efficient deadlock detection technique has been defined. This technique is tailored to the eight primitives, which are not sufficient to model many realistic designs. We exhibit two primitives, namely, an adaptive switch and a synchronization barrier, that cannot be expressed or analyzed using the current xMAS language and tools. Our main contribution is to automatically generate an efficient deadlock detection algorithm tailored to a given set of primitives. We define a set of core primitives and extension mechanisms for user-defined primitives. This creates a family of MaDL's together with a family of tailored and efficient deadlock detection algorithms. We prove that the automatically generated algorithms are correct by construction, i.e., they correctly detect deadlocks in all fabrics defined in the language for which they are generated. These algorithms handle message dependencies, counters, virtual channels, parametric buffer sizes, and many other aspects of micro-architectural models. The effectiveness of our approach is demonstrated on models with adaptive switches and synchronization barriers. Our approach automatically provides efficient deadlock detection for a large family of MaDL's.","PeriodicalId":184509,"journal":{"name":"2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126453308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Energy aware TLM platform simulation via RTL abstraction 基于RTL抽象的能量感知TLM平台仿真

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2012-11-01 DOI: 10.1109/HLDVT.2012.6418258

N. Bombieri, F. Fummi, V. Guarnieri, A. Acquaviva

{"title":"Energy aware TLM platform simulation via RTL abstraction","authors":"N. Bombieri, F. Fummi, V. Guarnieri, A. Acquaviva","doi":"10.1109/HLDVT.2012.6418258","DOIUrl":"https://doi.org/10.1109/HLDVT.2012.6418258","url":null,"abstract":"Energy consumption estimation is nowadays one of the most pressing concerns in the design of embedded systems. In order to provide power estimates, techniques have been developed to enable energy-aware simulation of CPU models at different abstraction levels, such as register-transfer level (RTL) and software through an instruction set simulator (ISS). However, the chosen abstraction level heavily affects the outcome of the simulation in terms of speed and accuracy. RTL simulations are more accurate because of their wealth in terms of implementation details, but require significant computation times. ISS simulations run much faster, but are affected by a loss of accuracy due to their software implementation. Transaction-level modeling (TLM) simulations provides an ideal trade-off between speed and accuracy, but they rely on the creation of a TLM platform which is usually not available and must be manually created. In this context, we propose a methodology to automatically abstract a starting RTL CPU description into a corresponding TLM description. The abstraction methodology preserves details required to perform an energy-aware simulation, such as timing accuracy and instruction counts.","PeriodicalId":184509,"journal":{"name":"2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115494790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Sequential equivalence checking of hard instances with targeted inductive invariants and efficient filtering strategies 具有目标归纳不变量和有效过滤策略的硬实例序列等价检验

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2012-11-01 DOI: 10.1109/HLDVT.2012.6418236

H. Nguyen, M. Hsiao

引用次数: 4

Emulation in post-silicon validation: It's not just for functionality anymore 后硅验证中的仿真:它不再仅仅是为了功能

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2012-11-01 DOI: 10.1109/HLDVT.2012.6418252

Kyle Balston, A. Hu, S. Wilton, Amir Nahir

{"title":"Emulation in post-silicon validation: It's not just for functionality anymore","authors":"Kyle Balston, A. Hu, S. Wilton, Amir Nahir","doi":"10.1109/HLDVT.2012.6418252","DOIUrl":"https://doi.org/10.1109/HLDVT.2012.6418252","url":null,"abstract":"FPGA-based emulation has emerged as an important tool in the overall validation process for an increasing number of large integrated circuits. Emulation gives the ability to validate a design using long-running, realistic tests, which are infeasible to perform using simulation. Traditionally, however, FPGA-based emulation has been used to validate only the functional behavior of an integrated circuit, since circuit-level properties (e.g., timing, noise margins, etc.) are obviously different between the FPGA emulation and the final integrated circuit. In this paper, we show that emulation can also be used as an important tool to assist validation of more than just functional behavior. In particular, we show how FPGA-based emulation can be used to evaluate the critical-path timing coverage of a validation plan, and show that the area and timing overheads are acceptable. We demonstrate this technique to measure the critical-path coverage of a complex SoC using common postsilicon validation tests - including booting Linux, and running targeted and random programs - giving valuable insight into the quality of such tests in covering the timing paths in a design post-silicon.","PeriodicalId":184509,"journal":{"name":"2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126791350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Eliminating race conditions in system-level models by using parallel simulation infrastructure 利用并行仿真基础设施消除系统级模型中的竞争条件

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2012-11-01 DOI: 10.1109/HLDVT.2012.6418253

Weiwei Chen, Che-Wei Chang, Xu Han, R. Dömer

{"title":"Eliminating race conditions in system-level models by using parallel simulation infrastructure","authors":"Weiwei Chen, Che-Wei Chang, Xu Han, R. Dömer","doi":"10.1109/HLDVT.2012.6418253","DOIUrl":"https://doi.org/10.1109/HLDVT.2012.6418253","url":null,"abstract":"For a top-down system design flow, a well-written specification model of an embedded system is crucial for its successful design and implementation. However, the task of writing a correct system-level model is difficult, as it involves, among other tasks, the insertion of parallelism. In this paper, we focus on ensuring model correctness under parallel execution. In particular, the model must be free of race conditions in all accesses to shared variables, so that a safe parallel implementation is possible. Eliminating race conditions is difficult because discrete event simulation often hides such flaws. In particular, the absence of simulation errors does not prove the correctness of the model. We propose to use advanced conflict analysis in the compiler, fast checking in a parallel simulator, and a novel race-condition diagnosis tool, that not only exposes all race conditions, but also locates where and when such problems occur. Our experiments have revealed a number of dangerous race conditions in existing embedded multi-media application models and enabled us to efficiently and safely eliminate these hazards.","PeriodicalId":184509,"journal":{"name":"2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115039181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Accurate profiling of oracles for self-checking time-constrained embedded software 准确的剖析为自检时间约束嵌入式软件的预言机

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2012-11-01 DOI: 10.1109/HLDVT.2012.6418249

Simone Bronuzzi, G. D. Guglielmo, F. Fummi, G. Pravadelli

{"title":"Accurate profiling of oracles for self-checking time-constrained embedded software","authors":"Simone Bronuzzi, G. D. Guglielmo, F. Fummi, G. Pravadelli","doi":"10.1109/HLDVT.2012.6418249","DOIUrl":"https://doi.org/10.1109/HLDVT.2012.6418249","url":null,"abstract":"One way to ensure the correct execution of embedded software is to keep debugging and testing even after shipping of the application, complemented with recovery/restart operations. In this context, the oracles, i.e., assertions and checkers, that have been widely used in the development process for design validation, can be deployed again in the final product. The application will use the oracles to monitor itself under the actual execution. In this way, erroneous out-of-the-specification behaviors can be captured at runtime. However, self-checking mechanisms come at a computational cost, which may affect time constrains of embedded software. Thus, the oracles shall be introduced while satisfying these time constraints. This work proposes a profiling approach for oracles in embedded software, which proves to be more accurate than traditional profiling approaches, e.g., statistical sampling techniques. Profiling the execution time of oracles permits to finely tune the execution rate of the application to avoid timing violation, and to increase application responsiveness. Experimental results have been carried out on an industrial deployment platform for real-time application, i.e., National Instruments PXI VeriStand.","PeriodicalId":184509,"journal":{"name":"2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134256232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A flexible modeling environment for a NoC-based multicore architecture 为基于noc的多核架构提供了灵活的建模环境

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2012-11-01 DOI: 10.1109/HLDVT.2012.6418256

R. Lemaire, S. Thuries, Frédéric Heitzmann

{"title":"A flexible modeling environment for a NoC-based multicore architecture","authors":"R. Lemaire, S. Thuries, Frédéric Heitzmann","doi":"10.1109/HLDVT.2012.6418256","DOIUrl":"https://doi.org/10.1109/HLDVT.2012.6418256","url":null,"abstract":"Following silicon technology improvements, Systems-on-Chip become more and more complex and require higher efforts for each design and validation steps. From architecture exploration to low-level hardware mechanism implementation, simulation platform are developed with different constraints in terms of speed performance or timing precision. The main issue is then to ensure consistency of the design all along the design flow process. In this paper, a NoC-based Multi-Processor System-on-Chip (MPSoC) architecture called GENEPY is introduced. The platform includes a mix of high-performance digital signal processing (DSP) cores, general-purpose processors (GPPs) and dedicated hardware accelerator all interconnected by a 2D-mesh Network-on-Chip (NoC). Associated with this architecture a flexible modeling environment is demonstrated. Built around a SystemC-TLM kernel, it integrates instruction set simulators and cosimulation wrappers and power estimators to adapt various types of user requirements from system architects to hardware designers and software developers in a common framework. Results are presented to assess the usability and potentiality of such modeling environment both for silicon implementation validation and for easier application mapping at early stage.","PeriodicalId":184509,"journal":{"name":"2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117297063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Post-silicon verification and debugging with control flow traces and patchable hardware 硅后验证和调试与控制流跟踪和可修补的硬件

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT) Pub Date : 2012-11-01 DOI: 10.1109/HLDVT.2012.6418250

M. Fujita

引用次数: 1