A flexible modeling environment for a NoC-based multicore architecture

Abstract

Following silicon technology improvements, Systems-on-Chip become more and more complex and require higher efforts for each design and validation steps. From architecture exploration to low-level hardware mechanism implementation, simulation platform are developed with different constraints in terms of speed performance or timing precision. The main issue is then to ensure consistency of the design all along the design flow process. In this paper, a NoC-based Multi-Processor System-on-Chip (MPSoC) architecture called GENEPY is introduced. The platform includes a mix of high-performance digital signal processing (DSP) cores, general-purpose processors (GPPs) and dedicated hardware accelerator all interconnected by a 2D-mesh Network-on-Chip (NoC). Associated with this architecture a flexible modeling environment is demonstrated. Built around a SystemC-TLM kernel, it integrates instruction set simulators and cosimulation wrappers and power estimators to adapt various types of user requirements from system architects to hardware designers and software developers in a common framework. Results are presented to assess the usability and potentiality of such modeling environment both for silicon implementation validation and for easier application mapping at early stage.