Embedded system verification through constraint-based scheduling

Abstract

Multiprocessor System-on-Chip (MPSoC) verification has become one of the main bottlenecks in the design process of embedded systems. Proving the correctness of a design efficiently is of extreme importance to reduce cost and time-to-market. Simulation is a common verification method, but complex systems usually require long simulation times. This work introduces Constraint Programming (CP) as a powerful tool for the verification of performance metrics of MPSoCs. Our methodology was evaluated using streaming applications mapped onto a target MPSoC. The resulting constraint-based scheduling problem allowed us to identify performance constraint violations in a fraction of the time required by simulation-based verification.