Automatic generation of Verilog bus transactors from natural language protocol specifications

Abstract

We present an approach to analyze natural language protocol specifications to generate Verilog bus transactors. We present a set of transaction concepts which are used, in text and formal models, to describe the behavior of transactions in a protocol. We employ semantic parsing to identify these transaction concepts in the natural language specification. The transaction concepts are translated into Verilog constructs to define Verilog tasks which model bus transactions defined in the protocol.