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2010 IEEE International Conference on Computer Design最新文献

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Boolean factoring with multi-objective goals 多目标布尔因子分解
2010 IEEE International Conference on Computer Design Pub Date : 2010-11-29 DOI: 10.1109/ICCD.2010.5647772
Mayler G. A. Martins, L. Rosa, A. B. Rasmussen, R. Ribas, A. Reis
{"title":"Boolean factoring with multi-objective goals","authors":"Mayler G. A. Martins, L. Rosa, A. B. Rasmussen, R. Ribas, A. Reis","doi":"10.1109/ICCD.2010.5647772","DOIUrl":"https://doi.org/10.1109/ICCD.2010.5647772","url":null,"abstract":"This paper introduces a new algorithm for Boolean factoring. The proposed approach is based on a novel synthesis paradigm, functional composition, which performs synthesis by associating simpler sub-solutions with minimum costs. The method constructively controls characteristics of final and intermediate functions, allowing the adoption of secondary criteria other than the number of literals for optimization. This multi-objective factoring algorithm presents interesting features and advantages when compared to previous works.","PeriodicalId":182350,"journal":{"name":"2010 IEEE International Conference on Computer Design","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128978827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 54
Efficient test response compaction for robust BIST using parity sequences 有效的测试响应压缩鲁棒BIST使用奇偶校验序列
2010 IEEE International Conference on Computer Design Pub Date : 2010-11-29 DOI: 10.1109/ICCD.2010.5647648
T. Indlekofer, Michael Schnittger, S. Hellebrand
{"title":"Efficient test response compaction for robust BIST using parity sequences","authors":"T. Indlekofer, Michael Schnittger, S. Hellebrand","doi":"10.1109/ICCD.2010.5647648","DOIUrl":"https://doi.org/10.1109/ICCD.2010.5647648","url":null,"abstract":"Nano-electronic circuits and systems are affected by increasing parameter variations and by an increasing susceptibility to soft errors. To improve yield and to compensate errors online, fault tolerance must be added to the design. Observing only the input/output behavior during manufacturing test would be too optimistic for such robust designs, whereas a purely structural test relying on DFT can be disturbed by soft errors and lead to an unnecessary yield loss. As a solution for circuits with time redundancy, “signature rollback” has been proposed, which partitions the test into shorter sessions and triggers a rollback after a faulty session to distinguish permanent from transient faults. It has been shown that both the test time and the yield loss decrease with the number of test sessions, but the hardware overhead increases. This paper proposes a solution with reduced hardware overhead by combining signature rollback with extreme space compaction. The new scheme is validated both analytically and by simulation experiments.","PeriodicalId":182350,"journal":{"name":"2010 IEEE International Conference on Computer Design","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129106227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
On mismatch number distribution of nanocrossbar logic mapping 纳米横条逻辑映射的错配数分布
2010 IEEE International Conference on Computer Design Pub Date : 2010-11-29 DOI: 10.1109/ICCD.2010.5647818
Yehua Su, Wenjing Rao
{"title":"On mismatch number distribution of nanocrossbar logic mapping","authors":"Yehua Su, Wenjing Rao","doi":"10.1109/ICCD.2010.5647818","DOIUrl":"https://doi.org/10.1109/ICCD.2010.5647818","url":null,"abstract":"Crossbar-based architectures are promising for the future nanoelectronic systems. Due to the inherent unreliability of nanotechnology, logic mapping onto highly defective crossbars needs to be performed on every chip. This posts significant challenge as the mapping problem is NP-complete. The complexity of the defect-tolerant logic mapping problems makes it hard to analyze runtime and model yield. This paper presents a new metric for evaluating the quality of the defect-tolerant logic mapping by tagging each mapping trial with a “score”, namely the mismatch number. Specifically, we look into the mismatch number distribution over: 1) crossbars having the same defect rate, 2) crossbars having the same defect number, and 3) a single crossbar with a given defect pattern. We show that the number of mismatches can be well modeled in probabilistic approaches, and the mismatch number distribution follows Normal/Poisson and Hypergeometric distribution, respectively. This new metric serves as the basis of performing runtime and yield analysis, which are difficult to estimate for logic mapping onto nanocrossbars. More importantly, the quantitative score for each underlying mapping trial serves as the basis in building the reliable nanocrossbar systems.","PeriodicalId":182350,"journal":{"name":"2010 IEEE International Conference on Computer Design","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116318653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Pulse latch based FSRs for low-overhead hardware implementation of cryptographic algorithms 基于脉冲锁存器的低开销加密算法硬件实现fsr
2010 IEEE International Conference on Computer Design Pub Date : 2010-11-29 DOI: 10.1109/ICCD.2010.5647756
S. Mansouri, E. Dubrova
{"title":"Pulse latch based FSRs for low-overhead hardware implementation of cryptographic algorithms","authors":"S. Mansouri, E. Dubrova","doi":"10.1109/ICCD.2010.5647756","DOIUrl":"https://doi.org/10.1109/ICCD.2010.5647756","url":null,"abstract":"In this paper, we address the problem of low-overhead implementation of Feedback Shift Registers (FSRs). We present a dynamic pulse latch which is based on transistors with two different channel lengths. The channel lengths are selected to make the latch suitable for replacing flip-flops in FSRs. The presented latch is 1.92 times smaller and 3.94 times less power consuming compared to the smallest standard flip-flop in the same technology. By re-implementing FSRs of Grain-80 stream cipher with the presented latch, we achieve 32.24% reduction in area, 36.77% reduction in total power, and 10.81% increase in the maximum clock frequency compared to the original, flip-flop based version of Grain-80. If, in addition, the static time borrowing technique is applied, we achieve an additional 25.5% increase in the maximum clock frequency at the expense of 4.68% smaller gain in area and 2.67% smaller gain in total power.","PeriodicalId":182350,"journal":{"name":"2010 IEEE International Conference on Computer Design","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117164956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
DfT optimization for pre-bond testing of 3D-SICs containing TSVs 含tsv的3d - sic粘结前测试的DfT优化
2010 IEEE International Conference on Computer Design Pub Date : 2010-11-29 DOI: 10.1109/ICCD.2010.5647651
Jia Li, D. Xiang
{"title":"DfT optimization for pre-bond testing of 3D-SICs containing TSVs","authors":"Jia Li, D. Xiang","doi":"10.1109/ICCD.2010.5647651","DOIUrl":"https://doi.org/10.1109/ICCD.2010.5647651","url":null,"abstract":"This paper proposes to provide testability for the breaking point produced by the Through-Silicon-Vias (TSVs) of 3D-Stacked ICs (3D-SICs) during pre-bond testing with low Design-for-Testability (DfT) cost. Different from prior solutions which utilize two additional wrapper cells for the breaking point at each TSV, this paper proposes to provide the testability of two ends of the TSVs respectively by reusing the existing Primary-Inputs (PIs)/ Primary-Outputs (POs) and Pseudo-PIs/Pseudo- POs (PPIs/PPOs). To further reduce the hardware overhead and enhance the efficiency of the proposed method, this paper has also proposed the metrics and algorithm on deciding the selecting order of the TSVs and the PIs/PPIs (POs/PPOs) to be reused. The experimental results on larger ITC'99 benchmark circuits validate the effectiveness of the proposed method.","PeriodicalId":182350,"journal":{"name":"2010 IEEE International Conference on Computer Design","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130479574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Data rate maximization by adaptive thresholding RF power management under renewable energy 可再生能源下自适应阈值射频功率管理的数据速率最大化
2010 IEEE International Conference on Computer Design Pub Date : 2010-11-29 DOI: 10.1109/ICCD.2010.5647812
Weiguo Tang, Lei Wang
{"title":"Data rate maximization by adaptive thresholding RF power management under renewable energy","authors":"Weiguo Tang, Lei Wang","doi":"10.1109/ICCD.2010.5647812","DOIUrl":"https://doi.org/10.1109/ICCD.2010.5647812","url":null,"abstract":"A new adaptive thresholding power management (ATPM) scheme is proposed to maximize the data rate of RF circuits in distributed embedded systems powered by renewable energy. Considering time-varying fading channels and statistical energy harvesting processes, we propose to turn on RF circuits only when the channel gain is higher than a threshold, and adjust the RF power according to the energy availability to improve the overall data rate. Exploiting the fact that the optimal threshold is a function of variable renewable energy subject to environmental changes, we adaptively adjust the threshold in accordance with renewable energy to improve energy efficiency. Simulation results based on solar energy indicate that the proposed ATPM scheme increases the average data rate by up to 60% compared with the scheme without channel gain thresholding, and achieves over 5X improvement in data rate over the constant power scheme with the same RF power consumption.","PeriodicalId":182350,"journal":{"name":"2010 IEEE International Conference on Computer Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134044160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Computational models for the age of multicore processing 多核处理时代的计算模型
2010 IEEE International Conference on Computer Design Pub Date : 2010-11-29 DOI: 10.1109/ICCD.2010.5647541
W. Paul
{"title":"Computational models for the age of multicore processing","authors":"W. Paul","doi":"10.1109/ICCD.2010.5647541","DOIUrl":"https://doi.org/10.1109/ICCD.2010.5647541","url":null,"abstract":"Industry is presently investigating the possibility to use commodity multicore processors connected by standard network components in safety critical systems like cars. In this scenario one clearly wants to be able to argue that a passenger on the rear seat trying to hack the car's entertainment system cannot shoot down the electronic chassis control and the engine control, although large portions of the hardware are shared. Any such argument - be it informal, a paper and pencil proof, or formally verified by a CAV system - has to consider the layers of the architecture of the car's computer system; it has to show that each layer provides a simulation between two adjacent computational models in the systems architecture and that these simulated models stay intact for all configurations and input sequences of the entire system. These models turn out to be far from obvious with very subtle and nontrivial modifications compared to classical textbook computer science.","PeriodicalId":182350,"journal":{"name":"2010 IEEE International Conference on Computer Design","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133606529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Feasibility study of dynamic Trusted Platform Module 动态可信平台模块的可行性研究
2010 IEEE International Conference on Computer Design Pub Date : 2010-11-29 DOI: 10.1109/ICCD.2010.5647705
A. Kanuparthi, M. Zahran, R. Karri
{"title":"Feasibility study of dynamic Trusted Platform Module","authors":"A. Kanuparthi, M. Zahran, R. Karri","doi":"10.1109/ICCD.2010.5647705","DOIUrl":"https://doi.org/10.1109/ICCD.2010.5647705","url":null,"abstract":"A Trusted Platform Module (TPM) authenticates general purpose computing platforms. This is done by taking platform integrity measurement and comparing it with a precomputed value at boot-time. Existing TPM architectures do not support run-time integrity checking of a program on the platform. Attackers can modify the program after it has been verified at the Time Of Check (TOC) and before its Time Of Use (TOU). In this paper we study the feasibility of integrating a dynamic on-chip TPM (DTPM) into the core processor pipeline to protect against TOCTOU attacks. We explore the challenges involved in designing DTPM and describe techniques to improve its performance. The proposed DTPM has 2.5% area overhead and 18% performance impact when compared to a single processor core without DTPM.","PeriodicalId":182350,"journal":{"name":"2010 IEEE International Conference on Computer Design","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132590906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Crosstalk modeling to predict channel delay in Network-on-Chips 片上网络中预测信道延迟的串扰建模
2010 IEEE International Conference on Computer Design Pub Date : 2010-11-29 DOI: 10.1109/ICCD.2010.5647684
A. Patooghy, S. Miremadi, Mansour Shafaei
{"title":"Crosstalk modeling to predict channel delay in Network-on-Chips","authors":"A. Patooghy, S. Miremadi, Mansour Shafaei","doi":"10.1109/ICCD.2010.5647684","DOIUrl":"https://doi.org/10.1109/ICCD.2010.5647684","url":null,"abstract":"Communication channels in Network-on-Chips (NoCs) are highly susceptible to crosstalk faults due to the use of nano-scale VLSI technologies in the fabrication of NoCs. Crosstalk faults cause variable timing delay in NoC channels based on the patterns of transitions appearing on the channels. This paper proposes an analytical model to estimate the timing delay of an NoC channel in the presence of crosstalk faults. The model calculates expected number of 4C, 3C, 2C, and 1C transition patterns to predict delay of a K-bit communication channel. The model is applicable for both non-protected channels and channels which are protected by crosstalk mitigation methods. Spice simulations are done in a wide range of working conditions to validate the proposed model. Delays extracted from the simulations are compared with those obtained from the model. Comparisons show that the proposed model accurately estimates the delay of NoC channels. In addition, the proposed model accelerates the evaluation phase of any crosstalk mitigation method by at least three orders of magnitude.","PeriodicalId":182350,"journal":{"name":"2010 IEEE International Conference on Computer Design","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115100862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A high performance router with dynamic buffer allocation for on-chip interconnect networks 为片上互连网络提供动态缓冲分配的高性能路由器
2010 IEEE International Conference on Computer Design Pub Date : 2010-11-29 DOI: 10.1109/ICCD.2010.5647657
Shubo Qi, Minxuan Zhang, Jinwen Li, Tianlei Zhao, Chengyi Zhang, Shaoqing Li
{"title":"A high performance router with dynamic buffer allocation for on-chip interconnect networks","authors":"Shubo Qi, Minxuan Zhang, Jinwen Li, Tianlei Zhao, Chengyi Zhang, Shaoqing Li","doi":"10.1109/ICCD.2010.5647657","DOIUrl":"https://doi.org/10.1109/ICCD.2010.5647657","url":null,"abstract":"With the number of processor cores increasing in chip multi-processors (CMPs) and global wire delays increasing, networks on chip have been gaining wide acceptance for on-chip inter-core communication. This paper introduces a low latency Dynamic Virtual Output Queues Router (DVOQR), which can reduce the router latency to two cycles by leveraging look-ahead routing computation and virtual output address queues scheme. Simulation results show that network throughput on a 4×4 mesh increases by up to 46.9% and 28.6%, compared to wormhole router and virtual channel router, and that DVOQR outperforms doubled buffer virtual channel router by 1.9% under same input speedup. Network zero-load-latency also decreases by 25.6% and 41% respectively under random traffic. The results with place and route used by Cadence Encounter in TSMC 65nm technology display that the frequency of DVOQR can reach 1.4 GHz, the cell area of the router is only 0.424mm2 and the power consumption is 274 mw under the 50% injection rate.","PeriodicalId":182350,"journal":{"name":"2010 IEEE International Conference on Computer Design","volume":"432 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132759154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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