Efficient test response compaction for robust BIST using parity sequences

Abstract

Nano-electronic circuits and systems are affected by increasing parameter variations and by an increasing susceptibility to soft errors. To improve yield and to compensate errors online, fault tolerance must be added to the design. Observing only the input/output behavior during manufacturing test would be too optimistic for such robust designs, whereas a purely structural test relying on DFT can be disturbed by soft errors and lead to an unnecessary yield loss. As a solution for circuits with time redundancy, “signature rollback” has been proposed, which partitions the test into shorter sessions and triggers a rollback after a faulty session to distinguish permanent from transient faults. It has been shown that both the test time and the yield loss decrease with the number of test sessions, but the hardware overhead increases. This paper proposes a solution with reduced hardware overhead by combining signature rollback with extreme space compaction. The new scheme is validated both analytically and by simulation experiments.