2010 IEEE International Conference on Computer Design最新文献_第3页

Efficient provably good OPC modeling and its applications to interconnect optimization 高效且良好的OPC建模及其在互连优化中的应用

2010 IEEE International Conference on Computer Design Pub Date : 2010-11-29 DOI: 10.1109/ICCD.2010.5647713

Shih-Lun Huang, Chung-Wei Lin, Yao-Wen Chang

{"title":"Efficient provably good OPC modeling and its applications to interconnect optimization","authors":"Shih-Lun Huang, Chung-Wei Lin, Yao-Wen Chang","doi":"10.1109/ICCD.2010.5647713","DOIUrl":"https://doi.org/10.1109/ICCD.2010.5647713","url":null,"abstract":"Optical Proximity Correction (OPC) is the most popular technique to handle design shape distortions arising from subwavelength lithography. Existing OPC models are typically very computationally expensive and thus not efficient to be incorporated for layout optimization. In this paper, we present an efficient, yet sufficiently accurate OPC cost model which can predict the optimal location of a wire segment for OPC optimization and give an upper bound of the interference amount, guaranteeing that the interference amount is never underestimated. Based on this cost model, we propose an OPC-aware wire perturbation algorithm for post-layout interconnect optimization. We show that the effects of wire perturbation have the concavity or monotonicity property which can dramatically reduce the search space for finding the optimal location of each wire for OPC optimization. Further, we can incrementally update the OPC cost of a wire by recomputing only the affected wires because of the property of superposition of our model. Experimental results show that our algorithm can efficiently obtain much better OPC results than a state-of-the-art OPC-friendly router, based on a leading commercial OPC tool.","PeriodicalId":182350,"journal":{"name":"2010 IEEE International Conference on Computer Design","volume":"329 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116123330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Optimal power/performance pipelining for error resilient processors 最优的功率/性能流水线的错误弹性处理器

2010 IEEE International Conference on Computer Design Pub Date : 2010-11-29 DOI: 10.1109/ICCD.2010.5647702

Nicolas Zea, J. Sartori, Ben Ahrens, Rakesh Kumar

引用次数: 4

Helia: Heterogeneous Interconnect for Low Resolution Cache Access in snoop-based chip multiprocessors 基于窥探的芯片多处理器中低分辨率缓存访问的异构互连

2010 IEEE International Conference on Computer Design Pub Date : 2010-11-29 DOI: 10.1109/ICCD.2010.5647589

Ali Shafiee, Narges Shahidi, A. Baniasadi

引用次数: 2

Design and implementation of a special purpose embedded system for neural machine interface 神经机器接口专用嵌入式系统的设计与实现

2010 IEEE International Conference on Computer Design Pub Date : 2010-11-29 DOI: 10.1109/ICCD.2010.5647801

Xiaorong Zhang, H. Huang, Qing Yang

引用次数: 6

Threads vs. caches: Modeling the behavior of parallel workloads 线程与缓存:模拟并行工作负载的行为

2010 IEEE International Conference on Computer Design Pub Date : 2010-11-29 DOI: 10.1109/ICCD.2010.5647747

Zvika Guz, O. Itzhak, I. Keidar, A. Kolodny, A. Mendelson, U. Weiser

引用次数: 24

LMS-based low-complexity game workload prediction for DVFS 基于lms的DVFS低复杂度游戏工作负荷预测

2010 IEEE International Conference on Computer Design Pub Date : 2010-11-29 DOI: 10.1109/ICCD.2010.5647675

Benedikt Dietrich, S. Nunna, Dip Goswami, S. Chakraborty, M. Gries

{"title":"LMS-based low-complexity game workload prediction for DVFS","authors":"Benedikt Dietrich, S. Nunna, Dip Goswami, S. Chakraborty, M. Gries","doi":"10.1109/ICCD.2010.5647675","DOIUrl":"https://doi.org/10.1109/ICCD.2010.5647675","url":null,"abstract":"While dynamic voltage and frequency scaling (DVFS) based power management has been widely studied for video processing, there is very little work on game power management. Recent work on proportional-integral-derivative (PID) controllers fro predicting game workload used hand-turned PID controller gains on relatively short game plays. This left open questions on the robustness of the PID controller and how sensitive the prediction quality is on the choice of the gain values, especially for long game plays involving different scenarios and scene changes. In this paper we propose a Least Mean Squares (LMS) Linear Predictor, which is a regression model commonly used for system parameter identification. Our results show that game workload variation can be estimated using a linear-in-parameters (LIP) model. This observation dramatically reduces the complexity of parameter estimation as the LMS Linear Predictor learns the relevant parameters of the model iteratively as the game progresses. The only parameter to be tuned by the system designer is the learning rate, which is relatively straightforward. Our experimental results using the LMS Linear Predictor show comparable power savings and game quality with those obtained from a highly-tuned PID controller.","PeriodicalId":182350,"journal":{"name":"2010 IEEE International Conference on Computer Design","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131176025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30

SWIFT: A SWing-reduced interconnect for a Token-based Network-on-Chip in 90nm CMOS SWIFT:用于90纳米CMOS中基于令牌的片上网络的swing减少互连

2010 IEEE International Conference on Computer Design Pub Date : 2010-11-29 DOI: 10.1109/ICCD.2010.5647666

T. Krishna, J. Postman, Christopher Edmonds, L. Peh, P. Chiang

引用次数: 59

Towards cool and reliable digital systems: RT level CED techniques with runtime adaptability 走向酷而可靠的数字系统:具有运行时适应性的RT级CED技术

2010 IEEE International Conference on Computer Design Pub Date : 2010-11-29 DOI: 10.1109/ICCD.2010.5647625

Yu Liu, Kaijie Wu

引用次数: 3

Bandwidth optimization in asynchronous NoCs by customizing link wire length 通过自定义链路长度来优化异步noc中的带宽

2010 IEEE International Conference on Computer Design Pub Date : 2010-11-29 DOI: 10.1109/ICCD.2010.5647660

Junbok You, Daniel Gebhardt, K. Stevens

引用次数: 10

A voting-based working set assessment scheme for dynamic cache resizing mechanisms 一种基于投票的动态缓存调整机制的工作集评估方案

2010 IEEE International Conference on Computer Design Pub Date : 2010-11-29 DOI: 10.1109/ICCD.2010.5647599

Masayuki Sato, Ryusuke Egawa, H. Takizawa, Hiroaki Kobayashi

{"title":"A voting-based working set assessment scheme for dynamic cache resizing mechanisms","authors":"Masayuki Sato, Ryusuke Egawa, H. Takizawa, Hiroaki Kobayashi","doi":"10.1109/ICCD.2010.5647599","DOIUrl":"https://doi.org/10.1109/ICCD.2010.5647599","url":null,"abstract":"Considering the trade-off between performance and power consumption has become significantly important in multi-core processor design. Under this situation, one promising approach is to employ a power-aware dynamic cache partitioning mechanism. This mechanism individually manages activation of each cache way, and exclusively allocates the minimum number of required ways to each thread. In the mechanism, an appropriate number of ways for a thread is decided based on locality assessment. However, sampling results of cache accesses that are used for locality assessment are disturbed by exceptional behaviors of cache accesses, which happen in a very short period. Such sampling results may change locality assessment results to ones that are not along with the overall trend in a long access-sampling period. These assessment results will excessively adapt the cache to exceptional behaviors, and deteriorate energy efficiency. To avoid such excessive adaptation by the exceptional behaviors, this paper proposes a voting-based working set assessment scheme, in which the number of activated ways is adjusted based on majority voting of locality assessment of several short sampling periods. By using the majority voting, the proposed scheme can identify the periods including exceptional behaviors, and ignore the assessment results of these periods. As a result, the proposed scheme makes the cache resizing mechanism more stable and robust. The experimental results indicate that the proposed scheme can reduce energy consumption by up to 24%, and 10% on an average without significant performance degradation in multi-thread execution on a 2-core CMP.","PeriodicalId":182350,"journal":{"name":"2010 IEEE International Conference on Computer Design","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121313551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7