2010 IEEE International Conference on Computer Design最新文献

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M5 based EDGE architecture modeling 基于M5的EDGE架构建模
2010 IEEE International Conference on Computer Design Pub Date : 2010-10-01 DOI: 10.1109/ICCD.2010.5647735
Pengfei Gou, Qingbo Li, Yinghan Jin, Qi Zheng, Bing Yang, Mingyan Yu, Jinxiang Wang
{"title":"M5 based EDGE architecture modeling","authors":"Pengfei Gou, Qingbo Li, Yinghan Jin, Qi Zheng, Bing Yang, Mingyan Yu, Jinxiang Wang","doi":"10.1109/ICCD.2010.5647735","DOIUrl":"https://doi.org/10.1109/ICCD.2010.5647735","url":null,"abstract":"EDGE (Explicit Data Graph Execution) architectures, a class of architectures distinct from traditional RISC and CISC architectures, have advantages that align well with current technology trends such as power limitations and the need for adaptive exploitation of parallelism. To better understand the architectural and microarchitectural design spaces of EDGE architectures, we have developed a flexible M5-based simulator for EDGE architectures. m5_edge includes a general high-level timing model and ISA support of one specific EDGE ISA. The high-level timing model is not designed to target a specific implementation but common characteristics of EDGE architectures, permitting faster development of a range of microarchitectures. The M5 infrastructure was used because of its high functionality and performance fidelity. The specific EDGE ISA we support is the TRIPS ISA, due to its well-specified ISA and relatively mature compiler. m5_edge can execute binaries generated by the TRIPS toolchain and provides a high-level simulation template for EDGE architectures. Our experimental results show that the difference in execution cycles of m5_edge is within 11% on average, compared to the cycle-accurate simulator provided by the TRIPS group. Thus, m5_edge benefits from both the flexible infrastructure of M5 and acceptable model accuracy, while maintaining both reasonable simulation speed and the ability to quickly explore EDGE-based microarchitectural design spaces.","PeriodicalId":182350,"journal":{"name":"2010 IEEE International Conference on Computer Design","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114639444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
VEDA: Variation-aware energy-efficient Discrete Wavelet Transform architecture VEDA:变化感知节能离散小波变换架构
2010 IEEE International Conference on Computer Design Pub Date : 1900-01-01 DOI: 10.1109/ICCD.2010.5647753
Vaibhav Gupta, G. Karakonstantis, Debabrata Mohapatra, K. Roy
{"title":"VEDA: Variation-aware energy-efficient Discrete Wavelet Transform architecture","authors":"Vaibhav Gupta, G. Karakonstantis, Debabrata Mohapatra, K. Roy","doi":"10.1109/ICCD.2010.5647753","DOIUrl":"https://doi.org/10.1109/ICCD.2010.5647753","url":null,"abstract":"In this paper, we present a unified approach to an energy-efficient variation-tolerant design of Discrete Wavelet Transform (DWT) in the context of image processing applications. It is to be noted that it is not necessary to produce exactly correct numerical outputs in most image processing applications. We exploit this important feature and propose a design methodology for DWT which shows energy quality tradeoffs at each level of design hierarchy starting from the algorithm level down to the architecture and circuit levels by taking advantage of the limited perceptual ability of the Human Visual System. A unique feature of this design methodology is that it guarantees robustness under process variability and facilitates aggressive voltage over-scaling. Simulation results show significant energy savings (74% – 83%) with minor degradations in output image quality and avert catastrophic failures under process variations compared to a conventional design.","PeriodicalId":182350,"journal":{"name":"2010 IEEE International Conference on Computer Design","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129935352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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