Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002最新文献

Hardware-software co-adaptation for data-intensive embedded applications 数据密集型嵌入式应用的软硬件协同适应

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-08-07 DOI: 10.1109/ISVLSI.2002.1016868

I. Kadayif, M. Kandemir, N. Vijaykrishnan, M. J. Irwin

{"title":"Hardware-software co-adaptation for data-intensive embedded applications","authors":"I. Kadayif, M. Kandemir, N. Vijaykrishnan, M. J. Irwin","doi":"10.1109/ISVLSI.2002.1016868","DOIUrl":"https://doi.org/10.1109/ISVLSI.2002.1016868","url":null,"abstract":"By studying energy and performance behavior of six array-dominated benchmarks, we observed that each nest in these applications works best with a specific cache configuration and optimization strategy. We also observed that cache configurations and optimization strategies required by different nests are, in general, different from each other. Based on this observation, in this paper, we propose a search space-based optimization for reducing energy consumption and improving performance. Specifically, we study potential benefits of a hardware-software co-adaptation scheme where cache configuration and optimization strategy are modified in the course of execution. Note that this is one step beyond determining just a suitable combination of (optimized) code/cache configuration which is valid throughout the execution of the application. The idea in co-adaptation is to ensure that each nested loop works with a cache configuration most suitable for it from the perspective of a given objective criterion. It should be noted, however, that dynamic cache reconfiguration does not come for free; it has both energy and performance costs which also need to be accounted for.","PeriodicalId":177982,"journal":{"name":"Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002","volume":"189 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132867925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Temperature variable supply voltage for power reduction 温度可变电源电压，减少功率

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-08-07 DOI: 10.1109/ISVLSI.2002.1016877

K. Shakeri, J. Meindl

引用次数: 19

Impact of technology scaling in the clock system power 技术缩放对时钟系统功耗的影响

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-08-07 DOI: 10.1109/ISVLSI.2002.1016875

D. Duarte, N. Vijaykrishnan, M. J. Irwin

引用次数: 46

An efficient partitioning algorithm of combinational CMOS circuits 一种有效的组合CMOS电路分划算法

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-08-07 DOI: 10.1109/ISVLSI.2002.1016890

B. Shaer, Khaled Dib

引用次数: 9

VLSI implementation for MAC-level DWT architecture mac级DWT架构的VLSI实现

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-08-07 DOI: 10.1109/ISVLSI.2002.1016882

Shiuh-Rong Huang, Lan-Rong Dung

引用次数: 1

Datapath scheduling using dynamic frequency clocking 使用动态频率时钟的数据路径调度

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-08-07 DOI: 10.1109/ISVLSI.2002.1016876

S. Mohanty, N. Ranganathan, V. Krishna

引用次数: 40

Improving structural FSM traversal by constraint-satisfying logic simulation 基于约束满足逻辑仿真的结构FSM遍历改进

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-08-07 DOI: 10.1109/ISVLSI.2002.1016889

Markus Wedler, D. Stoffel, W. Kunz

引用次数: 5

A network on chip architecture and design methodology 片上网络架构和设计方法

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-08-07 DOI: 10.1109/ISVLSI.2002.1016885

Shashi Kumar, A. Jantsch, Mikael Millberg, Johnny Öberg, J. Soininen, M. Forsell, Kari Tiensyrjä, A. Hemani

{"title":"A network on chip architecture and design methodology","authors":"Shashi Kumar, A. Jantsch, Mikael Millberg, Johnny Öberg, J. Soininen, M. Forsell, Kari Tiensyrjä, A. Hemani","doi":"10.1109/ISVLSI.2002.1016885","DOIUrl":"https://doi.org/10.1109/ISVLSI.2002.1016885","url":null,"abstract":"We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NOC), includes both the architecture and the design methodology. The NOC architecture is a m/spl times/n mesh of switches and resources are placed on the slots formed by the switches. We assume a direct layout of the 2-D mesh of switches and resources providing physical- and architectural-level design integration. Each switch is connected to one resource and four neighboring switches, and each resource is connected to one switch. A resource can be a processor core, memory, an FPGA, a custom hardware block or any other intellectual property (IP) block, which fits into the available slot and complies with the interface of the NOC. The NOC architecture essentially is the onchip communication infrastructure comprising the physical layer, the data link layer and the network layer of the OSI protocol stack. We define the concept of a region, which occupies an area of any number of resources and switches. This concept allows the NOC to accommodate large resources such as large memory banks, FPGA areas, or special purpose computation resources such as high performance multi-processors. The NOC design methodology consists of two phases. In the first phase a concrete architecture is derived from the general NOC template. The concrete architecture defines the number of switches and shape of the network, the kind and shape of regions and the number and kind of resources. The second phase maps the application onto the concrete architecture to form a concrete product.","PeriodicalId":177982,"journal":{"name":"Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122324159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1343

Simultaneous optimization of driving buffer and routing switch sizes in an FPGA using an iso-area approach 在FPGA中使用等面积方法同时优化驱动缓冲区和路由开关大小

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-08-07 DOI: 10.1109/ISVLSI.2002.1016870

V. Chandra, H. Schmit

引用次数: 7

Multi-output timed Shannon circuits 多输出定时香农电路

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-08-07 DOI: 10.1109/ISVLSI.2002.1016873

M. Thornton, R. Drechsler, D. M. Miller

引用次数: 3