Temperature variable supply voltage for power reduction

The scaling trend of MOSFETs requires the supply and the threshold voltages to be reduced in future generations. Although the supply voltage is reduced, the total power dissipation and the static power of the chip are increased. Power dissipation is one of the limiting factors in achieving the highest performance of a chip. Therefore, new power reduction techniques are required. In this paper a new technique is introduced to reduce the power consumption. In this technique the supply voltage is changed dynamically as temperature changes. Using this technique, for 70 nm devices the total power consumption of the chip can be reduced by 24% and the static power can be reduced by 40%. This reduction is achieved without any change in the worst-case delay.