Simultaneous optimization of driving buffer and routing switch sizes in an FPGA using an iso-area approach

Abstract

In this paper, we analyze the gain from simultaneous sizing of driving buffers and routing switches on an FPGA interconnect performance. We show that it is not area feasible to build FPGAs with optimally sized interconnects. However, with constrained interconnect area, it is possible to significantly improve the speed of interconnects by simultaneously sizing the driving buffers and routing switches. Our experiments suggest that by simultaneously optimizing the routing resources, delay can be improved by 15-20%. We introduce the idea of iso-area optimization in which we find optimal sizing of routing resources within an overall area constraint. We also show that by making the routing architecture heterogeneous, in terms of routing switch size, we can further improve the performance of an FPGA by 1-12%.