Impact of technology scaling in the clock system power

Abstract

The clock distribution and generation circuitry is known to consume more than a quarter of the power budget of existing microprocessors. A previously derived clock energy model is briefly reviewed while a comprehensive framework for the estimation of systemwide (chip level) and clock sub-system power as function of technology scaling is presented. This framework is used to study and quantify the impact that various intensifying concerns associated with scaling (i.e., increased leakage currents, increased interwire capacitance) will have on clock energy and their relative impact on the overall system energy. The results obtained indicate that clock power will remain a significant contributor to the total chip power, as long as techniques are used to limit leakage power consumption.