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Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002最新文献

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Optimal supply and threshold scaling for subthreshold CMOS circuits 亚阈值CMOS电路的最佳电源和阈值缩放
Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-08-07 DOI: 10.1109/ISVLSI.2002.1016866
Alice Wang, A. Chandrakasan, S. Kosonocky
{"title":"Optimal supply and threshold scaling for subthreshold CMOS circuits","authors":"Alice Wang, A. Chandrakasan, S. Kosonocky","doi":"10.1109/ISVLSI.2002.1016866","DOIUrl":"https://doi.org/10.1109/ISVLSI.2002.1016866","url":null,"abstract":"With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits have been inadequate for high performance applications, but have been used in applications that require ultra low power dissipation. Many applications including medical and wireless applications, require ultra low power dissipation with low-to-moderate performance (10kHz-100MHz). In this work, using BSIM3 models, the performance and energy dissipation of 0.18-/spl mu/m CMOS circuits for the range of V/sub dd/ = 0.1-0.6V and V/sub th/ = 0-0.6V are analyzed to show that subthreshold CMOS circuits can be used in low performance applications. A simple characterization circuit is introduced which can be used to evaluate the performance and energy dissipation for a given process under varying activity. These results are useful in circuit design by giving insight into optimal voltage supply and threshold voltage operation for a given application specification.","PeriodicalId":177982,"journal":{"name":"Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002","volume":"163 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121743008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 211
Scalable VLSI architecture for GF(p) Montgomery modular inverse computation 用于GF(p) Montgomery模逆计算的可扩展VLSI架构
Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-04-25 DOI: 10.1109/ISVLSI.2002.1016874
A. Gutub, A. Tenca, Ç. Koç
{"title":"Scalable VLSI architecture for GF(p) Montgomery modular inverse computation","authors":"A. Gutub, A. Tenca, Ç. Koç","doi":"10.1109/ISVLSI.2002.1016874","DOIUrl":"https://doi.org/10.1109/ISVLSI.2002.1016874","url":null,"abstract":"Modular inverse computation is needed in several public key cryptographic applications. In this work, we present two VLSI hardware implementations used in the calculation of Montgomery modular inverse operation. The implementations are based on the same inversion algorithm, however, one is fixed (fully parallel) and the other is scalable. The scalable design is the novel modification performed on the fixed hardware to make it occupy a small area and operate within better or similar speed. Both hardware designs are compared based on their speed and area. The area of the scalable design is on average 42% smaller than the fixed one. The delay of the designs, however, depends on the actual data size and the maximum numbers the hardware can handle. As the actual data size approaches the hardware limit the scalable hardware speedup reduces in comparison to the fixed one, but still its delay is practical.","PeriodicalId":177982,"journal":{"name":"Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114420387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
A high speed shift-invariant wavelet transform chip for video compression 一种用于视频压缩的高速平移不变小波变换芯片
Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-04-25 DOI: 10.1109/ISVLSI.2002.1016886
Henry Y. H. Chuang, David P. Birch, Li-Chang Liu, Jong-Chih Chien, S. Levitan, Ching-Chung Li
{"title":"A high speed shift-invariant wavelet transform chip for video compression","authors":"Henry Y. H. Chuang, David P. Birch, Li-Chang Liu, Jong-Chih Chien, S. Levitan, Ching-Chung Li","doi":"10.1109/ISVLSI.2002.1016886","DOIUrl":"https://doi.org/10.1109/ISVLSI.2002.1016886","url":null,"abstract":"Wavelet-based video compression can provide improved codec and bit rates. The shift-variance problem of the discrete wavelet transform on image sequences, however, may cause large errors in motion estimation in the wavelet domain and thus degrade its performance of video compression. To make the wavelet transform of an image shift-invariant, a large amount of additional computation is required. For this reason a high-speed hardware implementation is necessary. This paper is focused on the VLSI design and implementation of a highly parallel shift-invariant wavelet transform chip. The RTL design, synthesis, simulations, and layout have been completed, and OKI Semiconductor, Inc. is fabricating the chip.","PeriodicalId":177982,"journal":{"name":"Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115113136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Automated synthesis of standard cells using genetic algorithms 使用遗传算法自动合成标准细胞
Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-04-25 DOI: 10.1109/ISVLSI.2002.1016888
A. Bahuman, B. Bishop, K. Rasheed
{"title":"Automated synthesis of standard cells using genetic algorithms","authors":"A. Bahuman, B. Bishop, K. Rasheed","doi":"10.1109/ISVLSI.2002.1016888","DOIUrl":"https://doi.org/10.1109/ISVLSI.2002.1016888","url":null,"abstract":"We have demonstrated the possibility of applying a genetic algorithm (GADO) to automate the design of a standard cell given only a behavioral description and optimization criteria such as power, area, speed or their combination. GADO maintains a population of potential standard cell designs. The designs are evaluated by (1) internal rules, (2) MAGIC for design rule checks and (3) SPICE for correctness of circuit behavior. Connections between transistors are encouraged by an influence check, which checks for broken connections and floating I/O nodes. Working inverters with arbitrary label placements are designed by evolution as a proof of concept.","PeriodicalId":177982,"journal":{"name":"Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127912364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A low power high performance distributed DCT architecture 一种低功耗高性能分布式DCT架构
Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-04-25 DOI: 10.1109/ISVLSI.2002.1016869
A. Shams, W. Pan, Archana Chidanandan, M. Bayoumi
{"title":"A low power high performance distributed DCT architecture","authors":"A. Shams, W. Pan, Archana Chidanandan, M. Bayoumi","doi":"10.1109/ISVLSI.2002.1016869","DOIUrl":"https://doi.org/10.1109/ISVLSI.2002.1016869","url":null,"abstract":"A new distributed arithmetic architecture, NEDA, is presented in this paper. NEDA is a low power optimized architecture based on the distributed arithmetic paradigm. In addition to low power performance, NEDA offers high speed and reduced area. In NEDA, inner product computational module has been proved, mathematically, to require only additions. Moreover, minimum number of additions is used by exploiting the redundancy in the adder array. Such properties have made a NEDA unit a basic computational module for high performance DSP architectures. A case study of 8/spl times/8 DCT NEDA-based architecture is analyzed. Savings exceeding 88% are achieved for the DCT implementation.","PeriodicalId":177982,"journal":{"name":"Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116331852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 IEEE计算机学会VLSI年度研讨会论文集。VLSI系统设计的新范例。ISVLSI 2002
Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 1900-01-01 DOI: 10.1109/ISVLSI.2002.1016864
M. A. Bayoumi
{"title":"Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002","authors":"M. A. Bayoumi","doi":"10.1109/ISVLSI.2002.1016864","DOIUrl":"https://doi.org/10.1109/ISVLSI.2002.1016864","url":null,"abstract":"The Symposium covers a range of topics: from VLSI circuits, systems, and design methods to system level design and system-on-chip issues, to bringing VLSI experience to new areas and technologies like nano- and molecular devices. Future design methodologies are also one of the key topics at the symposium, as well as new CAD tools to support them.","PeriodicalId":177982,"journal":{"name":"Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127024872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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