Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002最新文献_第2页

Speedup of self-timed digital systems using Early Completion 使用提前完成的自定时数字系统的加速

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-08-07 DOI: 10.1109/ISVLSI.2002.1016884

S. Smith

引用次数: 26

VLSI systems for embedded video 用于嵌入式视频的VLSI系统

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-08-07 DOI: 10.1109/ISVLSI.2002.1016865

W. Wolf, I. Özer, T. Lv

引用次数: 1

High-performance field programmable VLSI processor based on a direct allocation of a control/data flow graph 高性能现场可编程VLSI处理器基于控制/数据流图的直接分配

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-08-07 DOI: 10.1109/ISVLSI.2002.1016881

Naotaka Ohsawa, M. Hariyama, M. Kameyama

引用次数: 12

Accelerating retiming under the coupled-edge timing model 耦合边定时模型下的加速重定时

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-08-07 DOI: 10.1109/ISVLSI.2002.1016887

I. Neumann, K. Sulimma, W. Kunz

引用次数: 1

System design and power optimization for mobile computers 移动计算机的系统设计和电源优化

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-08-07 DOI: 10.1109/ISVLSI.2002.1016867

A. Smailagic, M. Ettus

引用次数: 31

Efficient adder circuits based on a conservative reversible logic gate 基于保守可逆逻辑门的高效加法器电路

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-08-07 DOI: 10.1109/ISVLSI.2002.1016879

J. Bruce, M. Thornton, L. Shivakumaraiah, P. S. Kokate, X. Li

引用次数: 201

A 1.2 V built-in architecture for high frequency on-line Iddq/delta Iddq test 1.2 V内置架构，用于高频在线Iddq/增量Iddq测试

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-08-07 DOI: 10.1109/ISVLSI.2002.1016891

S. Dragic, M. Margala

引用次数: 18

Noise tolerant low power dynamic TSPCL D flip-flops 耐噪低功耗动态TSPCL D触发器

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-08-07 DOI: 10.1109/ISVLSI.2002.1016880

M. Elgamel, T. Darwish, M. Bayoumi

{"title":"Noise tolerant low power dynamic TSPCL D flip-flops","authors":"M. Elgamel, T. Darwish, M. Bayoumi","doi":"10.1109/ISVLSI.2002.1016880","DOIUrl":"https://doi.org/10.1109/ISVLSI.2002.1016880","url":null,"abstract":"The extensive use of a dynamic circuit techniques for higher performance has already been implemented in many circuits like microprocessors. With the scaling down to deep submicron technology and the move towards dynamic circuit techniques, noise immunity is becoming an important metric like power, speed, and area. This paper proposes a technique to achieve low energy consumption in TSPCL D flip-flops. The paper studies some published flip-flops and carries out a modification that reduces the switching activity of some internal nodes, causing a big saving in power consumption. The proposed flip-flop is characterized and compared with those published ones for reliability and energy efficiency. Comparison for speed, power consumption, and noise tolerance is also presented. The average noise threshold energy (ANTE) and the energy normalized ANTE metrics are used for quantifying the noise immunity and energy efficiency, respectively of flip-flops. Results using 0.18 /spl mu/m CMOS technology and HSPICE for simulation, show that the proposed TSPCL D flip-flop achieves reduction in power dissipation ranging from 4.6% to 80% depending on the input pattern and the technology in use. The noise immunization curves show that the modified flip-flop is more susceptible to noise. Hence, one of the known noise immunization techniques should be applied.","PeriodicalId":177982,"journal":{"name":"Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133760098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

Force-directed scheduling for dynamic power optimization 动态功率优化的力导向调度

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-08-07 DOI: 10.1109/ISVLSI.2002.1016878

Suvodeep Gupta, S. Katkoori

{"title":"Force-directed scheduling for dynamic power optimization","authors":"Suvodeep Gupta, S. Katkoori","doi":"10.1109/ISVLSI.2002.1016878","DOIUrl":"https://doi.org/10.1109/ISVLSI.2002.1016878","url":null,"abstract":"We present a latency-constrained scheduling algorithm to optimize a design for dynamic power Usage of forces to model power is motivated by the force-directed scheduling (FDS) heuristic proposed by Paulin and Knight (1989). Given a dataflow graph (DFG) and an input data environment, we profile the DFG with representative data streams. Our algorithm reduces dynamic power by reducing switched capacitance inside resources. The switched capacitance of combinations among DFG operations, which could share a resource, and the probability of selecting such a combination, are evaluated. Switched capacitance inside a module is modeled as the spring constant k and probability of selecting the corresponding combination is modeled as the displacement x, in the force equation F=kx. Thus, a force is associated with each feasible combination corresponding to its power cost. Due to numerous possibilities, we obtain a distribution of forces whose mean, standard deviation, and skew are used to make a power-optimal scheduling decision. Compared to original FDS, our algorithm shows average power savings of 16.4% for the same throughput at the cost of a nominal area overhead.","PeriodicalId":177982,"journal":{"name":"Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130753775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

Optimal timing for skew-tolerant high-speed domino logic 可容斜高速骨牌逻辑的最佳时序

Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002 Pub Date : 2002-08-07 DOI: 10.1109/ISVLSI.2002.1016871

Seong-ook Jung, Ki-Wook Kim, S. Kang

引用次数: 2