Noise tolerant low power dynamic TSPCL D flip-flops

Abstract

The extensive use of a dynamic circuit techniques for higher performance has already been implemented in many circuits like microprocessors. With the scaling down to deep submicron technology and the move towards dynamic circuit techniques, noise immunity is becoming an important metric like power, speed, and area. This paper proposes a technique to achieve low energy consumption in TSPCL D flip-flops. The paper studies some published flip-flops and carries out a modification that reduces the switching activity of some internal nodes, causing a big saving in power consumption. The proposed flip-flop is characterized and compared with those published ones for reliability and energy efficiency. Comparison for speed, power consumption, and noise tolerance is also presented. The average noise threshold energy (ANTE) and the energy normalized ANTE metrics are used for quantifying the noise immunity and energy efficiency, respectively of flip-flops. Results using 0.18 /spl mu/m CMOS technology and HSPICE for simulation, show that the proposed TSPCL D flip-flop achieves reduction in power dissipation ranging from 4.6% to 80% depending on the input pattern and the technology in use. The noise immunization curves show that the modified flip-flop is more susceptible to noise. Hence, one of the known noise immunization techniques should be applied.